Abstract: A method and apparatus for flash EEPROM refresh is provided in which the control gate of a particular memory cell is read at an elevated control gate voltage (42). It is next determined whether the cell has been programmed (44). If the cell has been programmed, then the next memory cell is read (46). If it is initially determined that the cell has not been programmed (44), then the particular memory cell is read at a lowered control gate voltage (48). It is then finally determined whether the cell has been programmed (50). If it is determined that the cell has not been programmed, then the next cell is read (46). If it is determined that the cell has been programmed (50), then the memory is refreshed (52). After refresh, the next memory cell is read (46).

Abstract: A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

Abstract: A nonvolatile memory has pairs of cells in which each cell includes a control gate, a floating gate and a source/drain diffusion. A first cell in each of the pairs is producible to have one value of floating-gate to diffusion capacitance. A second cell in each of the pairs is producible to have a second value of floating-gate to diffusion capacitance different from the first value. The memory includes a first circuit for applying a first erasing pulse to the control gates and the diffusions of the first cells of the pairs and includes a second circuit for applying a second erasing pulse to the control gates and the diffusions of the second cells of the pairs. The first erasing pulse is adjustable to have a different magnitude than the second erasing pulse in order to narrow the margin of erased threshold voltages and thereby compensate for misalignment.

Abstract: A method and apparatus for negative wordline decoding in a flash EEPROM (10) is provided. In particular, a predecoder (26) generates a predecoding signal based on address and invert inputs. The predecoding signal is used to select wordlines in both positive and negative voltage decoding modes. Each wordline has associated with it a driver (28). The driver (28) receives the predecoding signal and is operable to drive the associated wordline high in response to the appropriate predecoding signal. Wordlines also have associated with them negative charge pumps (32). Each charge pump (32) is operable to drive the associated wordline negative when the driver (28) is not driving the wordline positive.

Abstract: A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for "ones" at low control gate voltage Vcc and for "zeros" at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.

Abstract: A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit for switching positive programming voltages and, optionally, a subcircuit for switching negative erasing voltages. The read-driver subcircuit may be constructed using relatively short-channel transistors for relatively high speed operation when connected to high-capacitance wordlines. On the other hand, the program-driver subcircuit may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit. P channel isolating transistors are used to isolate unused circuitry during operation. A voltage translator in the program-driver subcircuit has a transistor configuration that lessens the probability that the breakdown voltages of those transistors will be exceeded.

Abstract: A byte-wide memory has a plurality of redundant columns. Each redundant column is capable of being mapped to any one of a plurality of input buffers and output buffers in place of a defective column. Fuse match logic circuits store the addresses of defective columns. I/O fuse decoder circuits are coupled to the fuse match logic circuits and store information identifying the input and output buffers associated with each defective column. The redundant columns are selected in response to a portion of the column address signals which select nonredundant columns. When a received column address matches a stored column address, the redundant column selected by the portion of column address signals is mapped to the input and output buffer associated with the defective column in place of the defective column.

Abstract: One aspect of the present invention includes a circuit for detecting when an input voltage exceeds a predetermined threshold. The circuit for detecting includes an input for receiving the input voltage. Further, the circuit includes a plurality of switching devices, wherein each of the switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path. The plurality of switching devices includes three switching devices. The first switching device has a first terminal coupled to the input and a second terminal coupled to a first node. The second switching device has a first terminal coupled to the first node and a second terminal coupled to a second node. Finally, the third switching device has a first terminal coupled to the second node.

Abstract: A common connection to reduces the amount of chip area required to perform read and programming functions, particularly where signals such as read, programming, supply voltage and data signals are generated from remote locations on the memory chip. The common connection is made in an integrated circuit having a control circuit, a plurality of memory cell arrays having column lines, a sense amplifier circuit, and a programming circuit including at least first and second parts. At least one column of one memory cell array is selectively connected to a common line/node upon receiving at least a first signal from the control circuit. The first part of the programming circuit is selectively connected to the common line/node upon receiving a second signal from the control circuit. The second part of the programming circuit is connected to the common line/node upon receiving a third signal from the control circuit.

Abstract: A circuit and method for rapid removal of drain-column programming voltages from drain-column lines of a memory array. The circuit includes a resistor/transistor connected between a supply voltage and a common node, the resistor/transistor being enabled by a program enable signal. During the discharge operation, the source-drain paths of a driver transistors of the array connect column lines to reference potential. The gates of the driver transistors are coupled to the common node. An enabling transistor has a source-drain path connecting reference potential to the common node and has a gate connected to the program enable signal. The circuit includes at least one inverter, an OR circuit, and a bypass transistor. The bypass transistor has a source-drain path connected between the supply voltage and the common node and a gate coupled to the common node through the inverter and the OR circuit.

Abstract: A voltage level detecting circuit is presented having simplistic construction, stable circuit operation and few components. The circuit includes: a p-channel transistor; a resistor; a ground terminal; a first voltage supply terminal for receiving a fixed voltage level; a second voltage supply terminal for receiving a variable voltage level; and an output terminal.

Abstract: A switching circuit for selectively coupling a first power supply to a power bus includes a first input terminal for connection to the first power supply and a means for coupling said first input terminal to a first node. A first transistor has a first source/drain region coupled to the first node and a second source/drain region coupled to the power bus. The first transistor is on in response to a first control signal applied to its gate to couple the first node to the power bus. A bias circuit is coupled to the substrate of the first transistor to prevent forward biasing of a junction between its substrate and its second source/drain region when the first transistor is on.

Abstract: Apparatus for determining the field position (00, 01, 10, 11) of an integrated circuit (18) within a reticle area (12) which contains a plurality of such integrated circuits (14-20) includes a plurality of memory cells (76, 80) formed within the integrated circuit (18) for encoding the field position. Circuitry (40, 94, 100, 104, 106) is provided for reading the states of the memory cells to ascertain the field position.

Abstract: A test circuit for determining whether or not fuse-links of an integrated circuit have been opened or closed properly by, for example, a laser device. The test circuit of this invention, in one embodiment, includes a variable impedance, such as a P-channel transistor, connected between a voltage source and an output terminal, the impedance having one value with a first input applied to the variable impedance control terminal and having a second, larger value in response to a second input applied to the variable impedance control terminal. At least one programmable fuse-link and a gate are connected in series between the output terminal and a source of reference potential. A means for providing control inputs to the variable impedance is connected between a test mode input signal and the control terminal of the variable impedance. The means for providing control inputs to the P-channel transistor may include a second, current-mirror-connected P-channel transistor.

Abstract: A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline.

Abstract: Apparatus for verifying the state of a plurality of electrically programmable memory cells (30-70) includes first and second memory cells (36, 38) each having current paths with first and second ends. A memory cell state sense node (BL2) is coupled to the first ends. A first array source node (82) is coupled to a second end of the current path of the first cell (36). A second array source node (84) is coupled to a second end of the current path of the second cell (38). First circuitry (160-198) is provided for sensing a program verify state (DATA, WE). Decoded ground circuitry (150, 144, 142) couples a selected one of the first and second array source nodes (140) to a low voltage source (Vss) in response to the first circuitry sensing a program verify state (DATA, WE).

Abstract: Resistors are used as controlling devices to control the rate at which output buffer transistors are turned OFF and ON to control transient noise.

Abstract: The memory array circuit this invention provides connection of segmented bitlines to bitline decoding circuitry while, at the same time, providing connection of combined wordlines wordline decoding circuitry. The segmentation and decoding connections permit faster speed of operation with minimal or no area penalty. The area penalty is avoided by driving common wordlines in each of the segments, effectively increasing the wordline pitch at the wordline decoder, while at the same time decreasing the number of wordline decodes required. The segmentation also permits location of the decoder circuit away from the signal and routing decode outputs.

Abstract: A method for measuring the access time or speed of PROM devices is described. The PROM (10) includes a matrix of erased memory cells (30-70) each selectable by an address, and readable by a sense amplifier (112). The method comprises providing an invalid address and reading the level at the sense amplifier (112). A valid address is then provided, and the memory cell addressed is read. The above steps are repeated until all memory cells are read. In this manner, the time required to access an erased memory cell after accessing a programmed memory cell, as simulated by a nonexistent memory cell, may be measured.

Abstract: Apparatus for decoding a plurality of electrically programmable memory cells (30-70) comprises an array source driver circuit (72) for selectively connecting a first terminal (140) of a selected memory cell (152) to a program bias voltage or to ground. A bit line driver circuit (94-100, 120) selectively connects a second terminal (154) of said selected memory cell (152) to ground or to a read sense node (115). Reading is performed by connecting the first terminal (140) to ground and the second terminal (154) to the read sense node (115). Programming is performed by connecting the first terminal (140) to the program bias voltage and the second terminal (154) to ground.