Patents by Inventor John F. Schreck
John F. Schreck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110191655Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Applicant: Micron Technology, Inc.Inventors: John F. Schreck, Todd A. Dauenbaugh
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Patent number: 7945840Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: GrantFiled: February 12, 2007Date of Patent: May 17, 2011Assignee: Micron Technology, Inc.Inventors: John F. Schreck, Todd A. Dauenbaugh
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Publication number: 20100059898Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
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Publication number: 20080195894Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.Type: ApplicationFiled: February 12, 2007Publication date: August 14, 2008Inventors: John F. Schreck, Todd A. Dauenbaugh
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Patent number: 7400124Abstract: An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.Type: GrantFiled: February 15, 2005Date of Patent: July 15, 2008Assignee: Micron Technology, Inc.Inventor: John F Schreck
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Patent number: 7200052Abstract: An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.Type: GrantFiled: February 15, 2005Date of Patent: April 3, 2007Assignee: Micron Technology, Inc.Inventor: John F Schreck
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Patent number: 7126317Abstract: An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.Type: GrantFiled: February 15, 2005Date of Patent: October 24, 2006Assignee: Micron Technology, Inc.Inventor: John F Schreck
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Patent number: 7106637Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.Type: GrantFiled: January 8, 2004Date of Patent: September 12, 2006Assignee: Micron Technology, Inc.Inventors: Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, Roger D. Norwood, John F. Schreck
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Publication number: 20040141397Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.Type: ApplicationFiled: January 8, 2004Publication date: July 22, 2004Inventors: Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, Roger D. Norwood, John F. Schreck
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Publication number: 20040027108Abstract: An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.Type: ApplicationFiled: August 12, 2002Publication date: February 12, 2004Inventor: John F. Schreck
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Patent number: 6690606Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.Type: GrantFiled: March 19, 2002Date of Patent: February 10, 2004Assignee: Micron Technology, Inc.Inventors: Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, Roger D. Norwood, John F. Schreck
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Publication number: 20030179612Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.Type: ApplicationFiled: March 19, 2002Publication date: September 25, 2003Inventors: Simon J. Lovett, Cliff Zitlaw, Brian M. Shirley, Roger D. Norwood, John F. Schreck
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Patent number: 6556503Abstract: A circuit designed to hold wordlines inactive when adjacent wordlines are activated to limit errors due to capacitive coupling between wordlines. A space saving technique for maintaining wordlines inactive uses a common gate structure across a plurality of bleed transistors which weakly hold the associated wordlines to an inactive level. The bleed device holds the inactive wordline to an inactive level while consuming a very small current. While the bleed device holds the wordlines inactive with a weak current, the bleed device hold may be overcome by other devices driving the wordlines active with strong drive currents. The use of modulated control of bleed devices is based upon the physical arrangement and proximity of adjacent wordlines such as in odd/even layouts of wordline architectures.Type: GrantFiled: August 21, 2001Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventor: John F. Schreck
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Publication number: 20030039167Abstract: A circuit designed to hold wordlines inactive when adjacent wordlines are activated to limit errors due to capacitive coupling between wordlines. A space saving technique for maintaining wordlines inactive uses a common gate structure across a plurality of bleed transistors which weakly hold the associated wordlines to an inactive level. The bleed device holds the inactive wordline to an inactive level while consuming a very small current. While the bleed device holds the wordlines inactive with a weak current, the bleed device hold may be overcome by other devices driving the wordlines active with strong drive currents. The use of modulated control of bleed devices is based upon the physical arrangement and proximity of adjacent wordlines such as in odd/even layouts of wordline architectures.Type: ApplicationFiled: August 21, 2001Publication date: February 27, 2003Applicant: Micron Technology, Inc.Inventor: John F. Schreck
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Patent number: 6049483Abstract: Circuits for applying a programming voltage and erase voltage to memory cells in a nonvolatile memory device are disclosed. The reverse breakdown of p-n junctions within the memory cells is prevented by providing a clamping p-n junction in the path used to apply the program or erase voltage to the memory cells. The clamping p-n junction will breakdown before the p-n junctions within the memory cells, protecting the memory cells from the adverse effects of a reverse breakdown condition.Type: GrantFiled: August 3, 1999Date of Patent: April 11, 2000Assignee: Texas Instruments IncorporatedInventors: John F. Schreck, David J. McElroy, Brian W. Huber
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Patent number: 5835395Abstract: A memory device is presented having the option, using simple means, of using one basic chip for different pin-outs or chip configurations. The metal and pin-out option implementation are formed by: 1) a dual-function pad and associated circuitry with an option for either an Input/Output or an Input-only configuration and 2) rotation of the chip with respect to the orientation of the DIP (dual in-line package). The implementation of this invention has decreased area requirements and better performance capabilities than those of known prior-art implementations.Type: GrantFiled: June 28, 1993Date of Patent: November 10, 1998Assignee: Texas Instruments IncorporatedInventors: John F. Schreck, Richard A. Bussey
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Patent number: 5636226Abstract: A fault sensing circuit for detecting the state of at least one latch controlled by at least one control signal is provided. The circuit comprises an additional latch also controlled by the same control signal and receiving an input of a known value. The output of the additional latch is coupled to an I/O pin where an external circuit may monitor its logic state to determine the occurrence of a fault.Type: GrantFiled: January 9, 1995Date of Patent: June 3, 1997Assignee: Texas Instruments IncorporatedInventors: Phat C. Truong, John F. Schreck
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Patent number: 5513064Abstract: An input protection device is presented for improving I/O electrostatic discharge ESD tolerance. The present invention protects a selected device by providing a sufficient potential difference between the substrate and the source of the device in question to protect it against an electrostatic discharge. In one embodiment of the invention, a resistor is placed between the substrate and the internal V.sub.SS connection. All V.sub.SS to substrate contacts have to be removed for internal V.sub.SS busses to be maintained at a predetermined resistance between the substrate and V.sub.SS. In other embodiments of the invention, an active device is placed between the substrate and the internal V.sub.SS connection. As with the first described embodiment, all V.sub.SS to substrate contacts have to be removed for internal V.sub.SS busses to be maintained at a predetermined resistance between the substrate and V.sub.SS. The active device presents a high impedance when not powered on and is very conductive when powered on.Type: GrantFiled: March 6, 1995Date of Patent: April 30, 1996Assignee: Texas Instruments IncorporatedInventor: John F. Schreck
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Patent number: 5491658Abstract: A virtual ground memory includes an array of rows and columns of memory cells and a plurality of alternating first and second column lines. The cells in each column are coupled to a first column line and a second column line. A first decoder selects a plurality of first column lines in response to first decoded address signals and selects one of the selected plurality of first column lines in response to second decoded address signals.Type: GrantFiled: February 13, 1991Date of Patent: February 13, 1996Assignee: Texas Instruments IncorporatedInventors: John F. Schreck, Phat C. Truong
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Patent number: 5412603Abstract: The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory cell array while, at the same time, pumping the drain 12 of the selected cell 10 to a voltage greater than the voltage VCC, which may be 3 V, at the supply-voltage terminal of the memory cell array. The cell substrate W2 is pumped to a voltage close to the voltage of the source 11 and, optionally, below the voltage of the source 11. One or more simple charge-pump circuits convert the output of the voltage supply VCC to a source-drain voltage and current capable of programming the selected nonvolatile cell 10 by hot carrier injection.Type: GrantFiled: May 6, 1994Date of Patent: May 2, 1995Assignee: Texas Instruments IncorporatedInventors: John F. Schreck, Cetin Kaya, David J. McElroy