Abstract: A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test.

Abstract: A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.

Abstract: An integrated circuit is disclosed, including a circuit with a first type of FET having a first breakdown voltage (VBD), resulting from a first set of design and manufacturing process parameters and having VBD tracking characteristics resulting from a second set of design and manufacturing process parameters. The IC may include a trigger device circuit a having a trigger FET that may generate, in response to the supply voltage exceeding a specified maximum, a signal on a trigger device output, causing a clamping device to couple the supply voltage node to the ground, to reduce the supply voltage. The trigger FET may be of a second type having a second VBD less than the first VBD, resulting from modifications to the first set of design and manufacturing process parameters, and VBD tracking characteristics resulting from the second set of design and manufacturing process parameters.

Abstract: Approaches for a comparative ESD protection scheme are provided. An electrostatic discharge (ESD) clamping circuit includes: a discharge field effect transistor (FET) connected between a power supply node and ground; and a comparator that receives a divided power supply voltage at a first input and a reference voltage at a second input. The comparator outputs a first value that turns the discharge FET on when the divided power supply voltage is greater than the reference voltage. The comparator outputs a second value that turns the discharge FET off when the divided power supply voltage is less than or equal to the reference voltage.

Abstract: Various embodiments include an integrated circuit having: at least one waveguide disposed in a low refractive index layer; a splitter connected to the at least one waveguide, the splitter consisting of at least two signal paths; an optical signal detector connected to an end of each of the at least two signal paths; and an electrical disconnect member connected to each optical signal detector.

Abstract: A device includes a laterally diffused metal-oxide-semiconductor (LDMOS) device integrated with an optical modulator. An optical waveguide of the optical modulator includes a silicon-containing structure in a drift region of the LDMOS device.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: Disclosed are optoelectronic integrated circuit structures that incorporate a first optical waveguide, having a semiconductor core, indirectly coupled to a grating coupler through a second optical waveguide, having a dielectric core, in order provide a relatively large alignment tolerance. The dielectric core can comprise multiple dielectric layers above one end of the semiconductor core and extending laterally over an isolation region adjacent to that end. The grating coupler can include dielectric fins above the isolation region. Alternatively, the grating coupler can include semiconductor fins within the isolation region. Also disclosed herein are methods of forming such optoelectronic integrated circuit structures that can be readily integrated with complementary metal oxide semiconductor (CMOS) device processing and germanium photodetector processing.

Abstract: A device includes a laterally diffused metal-oxide-semiconductor (LDMOS) device integrated with an optical modulator. An optical waveguide of the optical modulator includes a silicon-containing structure in a drift region of the LDMOS device.

Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands.

Abstract: A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments.

Abstract: Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

Abstract: Checking the layout integrity includes the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature.

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

Abstract: An encapsulated sensors and methods of manufacture are disclosed herein. The method includes forming an amorphous or polycrystalline material in contact with a layer of seed material. The method further includes forming an expansion space for the amorphous or polycrystalline material. The method further includes forming an encapsulation structure about the amorphous or polycrystalline material. The method further includes crystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space.

Abstract: Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.

Abstract: A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.