Patents by Inventor John J. Ellis-Monaghan
John J. Ellis-Monaghan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8698244Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.Type: GrantFiled: December 10, 2009Date of Patent: April 15, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
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Publication number: 20140097434Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.Type: ApplicationFiled: October 4, 2012Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John J. Ellis-Monaghan, Michael J. Hauser, Zhong-Xiang He, Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Anthony K. Stamper
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Patent number: 8681254Abstract: The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.Type: GrantFiled: October 28, 2011Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Mark D. Jaffe
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Patent number: 8674474Abstract: A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers.Type: GrantFiled: September 23, 2013Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Kristin M. Ackerson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Yen L. Lim
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Patent number: 8658456Abstract: A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided.Type: GrantFiled: March 15, 2013Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
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Patent number: 8647913Abstract: A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.Type: GrantFiled: September 13, 2012Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: James William Adkisson, Jeffrey Peter Gambino, Robert Kenneth Leidy, John J. Ellis-Monaghan
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Publication number: 20140021516Abstract: A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers.Type: ApplicationFiled: September 23, 2013Publication date: January 23, 2014Applicant: INTERNATONAL BUSINESS MACHINES CORPORATIONInventors: Kristin M. ACKERSON, John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Yen L. LIM
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Publication number: 20140004687Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: International Business Machines CorporationInventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
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Patent number: 8610185Abstract: A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.Type: GrantFiled: January 8, 2013Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Andres Bryant, William F. Clark, Jr., John J. Ellis-Monaghan, Edward J. Nowak
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Patent number: 8610174Abstract: Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.Type: GrantFiled: November 30, 2011Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, David L. Harame, Qizhi Liu, John J. Pekarik
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Patent number: 8592268Abstract: An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.Type: GrantFiled: April 15, 2013Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
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Publication number: 20130299939Abstract: Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.Type: ApplicationFiled: May 11, 2012Publication date: November 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yoba Amoah, John J. Ellis-Monaghan, Roger C. Kuo, Molly J. Leitch, Zhihong Zhang
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Patent number: 8564067Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.Type: GrantFiled: February 21, 2013Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
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Publication number: 20130265068Abstract: A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.Type: ApplicationFiled: April 10, 2012Publication date: October 10, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yoba Amoah, John J. Ellis-Monaghan, Roger C. Kuo, Molly J. Leitch, Zhihong Zhang
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Patent number: 8551859Abstract: A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers.Type: GrantFiled: November 10, 2011Date of Patent: October 8, 2013Assignee: International Business Machines CorporationInventors: Kristin M. Ackerson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Yen L. Lim
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Publication number: 20130228835Abstract: An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.Type: ApplicationFiled: April 15, 2013Publication date: September 5, 2013Applicant: International Business Machines CorporationInventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Kirk D. PETERSON, Jed H. RANKIN
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Publication number: 20130200910Abstract: A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Applicant: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
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Publication number: 20130186754Abstract: A biosensor capacitor, including a dielectric layer; a first metal layer in the dielectric layer; a passivation layer over the dielectric layer and the first metal layer; an isolation layer over the passivation layer; a probe DNA electrode connected to the first metal layer; a counter electrode connected to the first metal layer wherein the counter electrode forms an enclosure around the probe DNA electrode; and a bond pad connected to the first metal layer.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kristin M. Ackerson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Yen Li Lim
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Patent number: 8492807Abstract: A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided.Type: GrantFiled: December 7, 2009Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
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Patent number: 8492214Abstract: Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.Type: GrantFiled: March 18, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Andres Bryant, William F. Clark, Jr., John J. Ellis-Monaghan, Edward J. Nowak