Patents by Inventor John J. Ellis-Monaghan

John J. Ellis-Monaghan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabricating polysilicon MOS devices and passive ESD devices
    Patent number: 9087808
    Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Michael J. Hauser, Zhong-Xiang He, Junjun Li, Xuefeng Liu, Anthony K. Stamper
  • SHIELDING STRUCTURES BETWEEN OPTICAL WAVEGUIDES
    Publication number: 20150192735
    Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, Jed H. RANKIN
  • Lateral silicon-on-insulator bipolar junction transistor process and structure
    Patent number: 9059230
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: John Z. Colt, Jr., John J. Ellis-Monaghan, Leah M. Pastel, Steven M. Shank
  • Dual L-shaped drift regions in an LDMOS device and method of making the same
    Patent number: 9059281
    Abstract: A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: David G. Brochu, Jr., John J. Ellis-Monaghan, Michael J. Hauser, Jeffrey B. Johnson, Xuefeng Liu
  • ENCAPSULATED SENSORS
    Publication number: 20150115270
    Abstract: An encapsulated sensors and methods of manufacture are disclosed herein. The method includes forming an amorphous or polycrystalline material in contact with a layer of seed material. The method further includes forming an expansion space for the amorphous or polycrystalline material. The method further includes forming an encapsulation structure about the amorphous or polycrystalline material. The method further includes crystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, William J. MURPHY, Kirk D. PETERSON, Steven M. SHANK
  • Vertically curved waveguide
    Patent number: 9002156
    Abstract: An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • Structure and method to create a damascene local interconnect during metal gate deposition
    Patent number: 8993428
    Abstract: A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin, Robert R. Robison
  • EOS PROTECTION CIRCUIT WITH FET-BASED TRIGGER DIODES
    Publication number: 20150085408
    Abstract: An integrated circuit is disclosed, including a circuit with a first type of FET having a first breakdown voltage (VBD), resulting from a first set of design and manufacturing process parameters and having VBD tracking characteristics resulting from a second set of design and manufacturing process parameters. The IC may include a trigger device circuit a having a trigger FET that may generate, in response to the supply voltage exceeding a specified maximum, a signal on a trigger device output, causing a clamping device to couple the supply voltage node to the ground, to reduce the supply voltage. The trigger FET may be of a second type having a second VBD less than the first VBD, resulting from modifications to the first set of design and manufacturing process parameters, and VBD tracking characteristics resulting from the second set of design and manufacturing process parameters.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Alain Loiseau
  • Biosensor capacitor
    Patent number: 8986523
    Abstract: A biosensor capacitor, including a dielectric layer; a first metal layer in the dielectric layer; a passivation layer over the dielectric layer and the first metal layer; an isolation layer over the passivation layer; a probe DNA electrode connected to the first metal layer; a counter electrode connected to the first metal layer wherein the counter electrode forms an enclosure around the probe DNA electrode; and a bond pad connected to the first metal layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kristin M. Ackerson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Yen Li Lim, Polina A. Razina
  • Fabricating polysilicon MOS devices and passive ESD devices
    Patent number: 8951893
    Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Michael J. Hauser, Zhong-Xiang He, Junjun Li, Xuefeng Liu, Anthony K. Stamper
  • Self-Aligned Gate Electrode Diffusion Barriers
    Publication number: 20150035076
    Abstract: A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
  • NANOPARTICLES FOR MAKING SUPERCAPACITOR AND DIODE STRUCTURES
    Publication number: 20150028449
    Abstract: Structures and methods of making a supercapacitor may include a first electrode comprising a first conductive plate and a 3-dimensional (3D) aggregate of sintered nanoparticles electrically connected one to another and to the first conductive plate. The supercapacitor may also include a dielectric formed on surfaces of the 3D aggregate of sintered nanoparticles. The supercapacitor may further include a second electrode comprising a solid second conductor that fills interstices between surfaces of the dielectric and electrically connects to a second conductive plate of a solid second conductor, disposed above an outermost portion of the dielectric.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Applicant: International Business Machines Corporation
    Inventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin
  • DUAL L-SHAPED DRIFT REGIONS IN AN LDMOS DEVICE AND METHOD OF MAKING THE SAME
    Publication number: 20150014771
    Abstract: A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: David G. Brochu, JR., John J. Ellis-Monaghan, Michael J. Hauser, Jeffrey B. Johnson, Xuefeng Liu
  • HIGH VOLTAGE LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR
    Publication number: 20150014769
    Abstract: A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: John J. ELLIS-MONAGHAN, Theodore J. LETAVIC, Santosh SHARMA, Yun SHI, Michael J. ZIERAK
  • Self-aligned gate electrode diffusion barriers
    Patent number: 8932920
    Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
  • JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY
    Publication number: 20150008487
    Abstract: Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Kevin K. Chan, John J. Ellis-Monaghan, David L. Harame, Qizhi Liu, John J. Pekarik
  • Junction field-effect transistor with raised source and drain regions formed by selective epitaxy
    Patent number: 8927357
    Abstract: Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, John J. Ellis-Monaghan, David L. Harame, Qizhi Liu, John J. Pekarik
  • Self-Aligned Gate Electrode Diffusion Barriers
    Publication number: 20140353759
    Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Applicant: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
  • Vertical bend waveguide coupler for photonics applications
    Patent number: 8903210
    Abstract: An optical waveguide structure may include a dielectric layer having a top surface, an optical waveguide structure, and an optical coupler embedded within the dielectric layer. The optical coupler may have both a substantially vertical portion that couples to the top surface of the dielectric layer and a substantially horizontal portion that couples to the optical waveguide structure. The substantially vertical portion and the substantially horizontal portion are separated by a curved portion.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • HIGH VOLTAGE LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR
    Publication number: 20140346596
    Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Inventors: John J. Ellis-Monaghan, Theodore J. Letavic, Santosh Sharma, Yun Shi, Michael J. Zierak