Abstract: Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.

Abstract: Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract: A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.

Abstract: A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure.

Abstract: Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

Abstract: A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

Abstract: A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions.

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract: A switched rail circuitry and modified cell structure is provided. More specifically, switched rail pixels with pull-up circuitry and a method of manufacture is provided. The pixel sensor circuit includes a switched rail line having a pull-up transistor, wherein the pull-up transistor is coupled to a supply voltage Vdd.

Abstract: CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates.

Abstract: The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

Abstract: A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface.

Abstract: The image quality of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

Abstract: A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.