Abstract: A semiconductor structure includes a back-end-of-line region including a first level of metal interconnects and a second level of metal interconnects separated by at least one interlayer dielectric layer, and a laser debonding test structure disposed in the back-end-of-line region. The laser debonding test structure includes a testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects, a set of test pads, and a set of vias, at least a subset of the set of vias extending from at least one test pad in the set of test pads to the testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects.

Abstract: A co-package optics structure is provided including a channel waveguide located in a glass substrate in which gradient period grating structures are located around the waveguide. Notably, the gradient period grating structures are located above, below and adjacent to each side of the waveguide. The waveguide and the gradient period grating structures are formed in the glass substrate using a laser which causes a change of the refractive index of the glass substrate in the areas in which laser exposure occurs.

Abstract: Co-packaged optical modules having high bandwidth density, low insertion loss, and solder reflow and reliability stress compatibility are provided. In one aspect, an optical module includes: a photonic integrated circuit attached to a substrate; a lid in direct contact with the substrate such that the photonic integrated circuit is present in between the substrate and the lid; optical waveguides attached to the photonic integrated circuit; and a ferrule attached to the optical waveguides. The lid can be present over the photonic integrated circuit, and directly contacts a top of the substrate. Conversely, the lid can be present below the photonic integrated circuit, and directly contacts a bottom of the substrate.

Abstract: A semiconductor structure includes a substrate, one or more electrical interconnects disposed in through-substrate vias extending vertically from an upper surface of the substrate to a lower surface of the substrate, one or more optical interconnects embedded in the substrate between the upper surface of the substrate and the lower surface of the substrate, and one or more optical connector pin holes extending from at least one side of the substrate between the upper surface of the substrate and the lower surface of the substrate.

Abstract: A semiconductor device includes a micro-ring resonator including a semiconductor ring having a heater portion and a modulator portion integrally formed therein, wherein the semiconductor ring includes a central portion and extended portions radially inside and radially outside the central portion, the extended portions being thinner than the central portion. Contacts connect to the extended portions of the heater portion and the modulator portion on a top and a bottom of the extended portions.

Abstract: A semiconductor device includes a first doped region of a first conductivity type and a second doped region of a second conductivity type different from the first conductivity type. A fusion bonded insulating layer is disposed between the first doped region and the second doped region, wherein the fusion bonded insulating layer forms a tuned depletion layer disposed between the first doped region and the second doped region to form a P-I-N junction.

Abstract: An apparatus including a substrate having a first surface, and a silicon interposer including a first surface and a second surface, wherein the first surface is connected to the first surface of the substrate. The apparatus also includes at least one stack including an artificial intelligence (AI) chiplet and a plurality of static random-access memories (SRAMs) stacked below the AI chiplet, wherein the at least one stack includes a top surface, a bottom surface, a first side surface and a second side surface, and the at least one stack is orthogonally attached by the first side surface to the second surface of the silicon interposer. The apparatus additionally includes a heat spreader surrounding the top surface, the bottom surface and the second side surface of the at least one stack.

Abstract: A semiconductor device includes a package substrate below a chip, the package substrate including upper build-up layer including a first plurality of power planes (VDD) and ground planes (GND) and a plurality of vias stacked vertically, a core layer, and lower build-up layers including a second plurality of VDD and GND, and a heat spreader layer over the chip. The heat spreader contacts the package substrate on both ends of the package substrate.

Abstract: A semiconductor structure includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.

Abstract: An exemplary interconnect structure includes a first substrate, a second substrate vertically below the first substrate; and an underlayer structure between and in contact with the first and second substrates in which the underlayer structure between and in contact with the first and second substrates, a conductive connector between and electrically connecting the first and second substrates. The underlayer structure comprises an electromagnetic curable layer and a high thermal conductive layer and the underlayer structure laterally surrounds the conductive connector.

Abstract: An apparatus including a plurality of vertically oriented insulating substrates, each substrate having a planar surface including a looped metal coil structure forming a planar inductor. Each of the substrates and formed planar inductors arranged in parallel and oriented vertically and adjacent each other in a series configuration for increased inductance. The formed inductor and substrate disposed vertically with respect to a horizontal axis and is inclined at an angle with respect to a vertical axis, the angle ranging between less than 90 degrees and greater than 0 degrees. A first magnetic material plate is disposed adjacent the planar inductor at a first planar surface of the substrate, and a second magnetic material plate disposed adjacent a second planar surface having a conductive trace connecting one end of the planar inductor, each first and second plate extending to limit a spatial extent of the magnetic fields created by the inductor.

Abstract: Structures including semiconductor chips (including chiplets and stacked chips/chiplets) are provided in which thermal heat removal is enhanced. The enhanced thermal heat removal is provided by utilizing interlayer dielectric (ILD) materials in at least one of the frontside back-end-of-the-line (BEOL) structure or the backside BEOL structure that have a high thermal conductivity.

Abstract: Semiconductor structures are provided in which heat spreading and thermal heat removal are improved by providing one or more heat removal paths in which heat spreading and thermal heat removal occurs leveraging horizontal direction and vertical directions and through reduced resistance of heat removal paths. Notably, heat is spread horizontally to the edges of the semiconductor structures and then the heat is removed vertically (up and/or down) from the semiconductor structures.

Abstract: A semiconductor testing device includes a test head including one or more probe heads, and one or more electrical connectors, a heating/cooling unit configured to spread and remove heat within at least one device of one or more devices under test, a handler wafer, and a fixture configured to support the handler wafer. The semiconductor testing device is configured to power up at least one device of the one or more devices under test during testing.

Abstract: A semiconductor device is provided for executing S-parameter testing. The semiconductor device includes a first layer comprising a device under test (DUT), a second layer including metallization, a third layer including a backside power distribution network (BSPDN), a signal pad and a connecting structure connecting the DUT to the signal pad via the metallization. The connecting structure includes a first connecting section by which the DUT is connected to the metallization and a second connecting section that extends from the metallization, through the first layer and through the third layer to the signal pad and by which the metallization is connected to the signal pad.

Abstract: A testing device includes N devices, and N?1 probe heads. N is an integer. An M-th probe head includes devices 1 to N-M electrically connected to each other. The M-th probe head is configured to test the M-th device, and M is an integer between 1 and N?1.

Abstract: A semiconductor optical waveguide is provided. The semiconductor optical waveguide has a semiconductor substrate. The semiconductor substrate defines opposing top and bottom surfaces, and an optical TSV extending substantially perpendicular to the top and bottom surfaces. The semiconductor waveguide further includes a waveguide optical circuit on the semiconductor substrate and optically connected to the optical TSV.

Abstract: A photonic device is provided and includes a waveguide, a p-n junction disposed on the waveguide, a first contact and a second contact. The p-n junction includes a quantum well between an upper portion doped with a first dopant and a lower portion doped with a second dopant. The first contact is doped with the first dopant and is disposed in contact with the upper portion. The second contact is doped with the second dopant and includes a first lead and a second lead. The first lead extends through a first side of the waveguide and terminates at a corresponding first side of the lower portion. The second lead extends through a second side of the waveguide and terminates at a corresponding second side of the lower portion.

Abstract: A semiconductor test structure includes a first surface comprising a plurality of first conductive contacts spaced apart from each other at a first pitch, and a second surface located opposite the first surface and comprising a plurality of second conductive contacts spaced apart from each other at a second pitch. The second pitch is less than the first pitch, and respective ones of the plurality of first conductive contacts are electrically connected to one or more respective ones of the plurality of second conductive contacts.

Abstract: A semiconductor package includes a substrate such as an organic laminate substrate having conductors for carrying signals and includes an integrated circuit (IC) chip, e.g., a 3-dimensional flip-chip IC stack mounted thereon. The flip-chip is electrically connected to exposed conductors at the organic laminate substrate for receiving power signals and ground therefrom. A thermally conductive heat spreader with a redistribution layer (RDL) of high thermal conductive material for power delivery and heat spreading is connected to a top surface of the IC chip. In an example, the RDL can electrically connect with the laminate below the chip and at the peripheral of the chip. The thermally conductive heat spreader structure is disposed on top the RDL layer for receiving, distributing and dissipating heat from a top surface of the RDL. The package enables improved power delivery, heat spreading and heat removal from a top side of the IC chip.