Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first semiconductor wafer and a second semiconductor wafer; and a bonding structure between the first semiconductor wafer and the second semiconductor wafer, where the bonding structure includes a first coaxial pad embedded in a first dielectric layer and a second coaxial pad embedded in a second dielectric layer, and the first coaxial pad is substantially aligned with the second coaxial pad. In one embodiment, the first coaxial pad includes an inner pad of substantially rectangular shape and an outer pad of substantially rectangular ring shape surrounding the inner pad.

Abstract: A semiconductor die package that has a substrate with one or more substrate layers with one or more substrate connections. A substrate layer can include one or more redistribution layers (RDLs). One or more dies (e.g., multiple dies) are disposed on a top substrate layer. The dies have one or more die external connections. Some of the die external connections are electrically connected to one or more substrate connections. One or more metallic dam stiffeners form into a dam enclosure that is disposed on and physically connected to the top substrate layer. The dam enclosure encloses one or more of the dies. The metallic dam enclosure has one or more electrically connected regions where the metallic dam enclosure is electrically connected to one or more of the substrate horizontal connections and one or more electrically insulated regions where the metallic dam enclosure is electrically insulated from one or more of the substrate horizontal connections and the substrate via connections.

Abstract: A heat spreader apparatus includes a first portion; a second portion; and a connecting portion between the first and second portions, with high-conductivity axes and a low-conductivity axis, the low-conductivity axis being directed between the first and second portions. In one or more embodiments, the first, second, and connecting portions are thermally anisotropic blocks, and the apparatus forms a rectangular prism.

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate wearable multiplatform sensing are provided. In one embodiment, a computer-implemented method comprises: measuring, by a system operatively coupled to a processor, wirelessly on a nail plate, physiological data of an entity; integrating and synchronizing, by the system, the physiological data with other physiological data from one or more devices to form integrated physiological data; and analyzing, by the system, the integrated physiological data to detect one or more disorders.

Abstract: Thin Film Batteries are made of battery layers. Each battery layer has a substrate with one or more battery structures on the substrate surface. The battery structures have a first electrode connection and a second electrode, a first electrode (e.g. a cathode or anode) is electrically connected to the first electrode connection and a second electrode (e.g. an anode or cathode) is electrically connected to the second electrode connection. An electrolyte is at least partial disposed between and electrically connected to the first and second electrodes. A first edge connection on one of the substrate edges is physically and electrically connected to the first electrode connection. A second edge connection on one of the substrate edges is physically and electrically connected to the second electrode connection. An electrically insulating lamination is disposed on the substrate and covers the components except for the first and second edge connections, connected to respective battery electrodes.

Abstract: An interposer sandwich structure includes a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes an attachment for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

Abstract: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Abstract: An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

Abstract: A carrier wafer, a structure, and a method are disclosed. The carrier wafer includes a wafer layer having a first surface and a second surface opposite the first surface, a first antireflective coating (ARC) layer positioned on the first surface of the wafer layer, a second ARC layer positioned on a surface of the first ARC layer opposite the wafer layer, and a thin release layer positioned on a surface of the second ARC layer opposite the first ARC layer. The structure includes the carrier wafer and a semiconductor device substrate positioned over the thin release layer of the carrier wafer. The method includes obtaining a wafer layer, forming an ARC layer on a surface of the wafer layer, forming a second ARC layer on a surface of the first ARC layer opposite the wafer layer, and forming a thin release layer on the second ARC layer.

Abstract: Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.

Abstract: Microbatteries and methods for forming microbatteries are provided. The microbatteries and methods address at least one or both of edge sealing issues for edges of a stack forming part of a microbatteries and overall sealing for individual cells for microbatteries in a batch process. A transferable solder molding apparatus and sealing structure are proposed in an example to provide a metal casing for a solid-state thin-film microbattery. An exemplary proposed process involves deposition or pre-forming low-temperature solder casing separately from the microbatteries. Then a thermal compression may be used to transfer the solder casing to each battery cell, with a handler apparatus in a batch process in an example. These exemplary embodiments can address the temperature tolerance constrain for solid state thin film battery during handling, metal sealing, and packaging.

Abstract: A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.

Abstract: A mechanism is provided in a data processing system to implement a multi-sensor health monitoring platform. The mechanism applies a machine learning model to predict patient needs and patient activity trends based on physiological features and activity features of the patient. The mechanism applies the machine learning model to predict energy requirements for a plurality of medical sensors based on the predicted patient needs and patient activity trends. The mechanism schedules recharging of the plurality of medical sensors based on the predicted energy requirements and identifying one or more sensors to set to an activate state based on the predicted patient needs and patient activity trends. The mechanism collecting sensor data from the one or more sensors and applies the machine learning model to generate a point-of-care recommendation based on the collected sensor data.

Abstract: A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.

Abstract: Multi-semiconductor chip modules that have a substrate with a substrate surface, one or more first substrate connections, and one or more second substrate connections. One or more first semiconductor chips (chips) has one or more larger first chip connections and one or more smaller first chip connections on a first chip bottom surface. One or more of the larger first chip connections physically and electrically connected to a respective first substrate connection. One or more second chips has one or more larger second chip connections and one or more smaller second chip connections on a second chip bottom surface. One or more of the larger second chip connections physically and electrically connected to a respective second substrate connection. A bridge has a bridge thickness, a bridge surface, and one or more bridge connections on the bridge surface. A first part of the bridge surface is under the first chip bottom surface and a second part of the bridge surface is under the second chip bottom surface.

Abstract: Techniques for colorimetric based test strip analysis and reader system are provided. In one aspect, a method of test strip analysis includes: illuminating a test strip wetted with a sample with select spectrums of light, wherein the test strip includes test pads that are configured to change color in the presence of an analyte in the sample; obtaining at least one digital image of the test strip; and analyzing color intensity from the at least one digital image against calibration curves to determine an analyte concentration in the sample with correction for one or more interference substances in the sample that affect the color intensity. A calibration method and a reader device are also provided.

Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.