Patents by Inventor John Knickerbocker
John Knickerbocker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11710669Abstract: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.Type: GrantFiled: May 25, 2020Date of Patent: July 25, 2023Assignee: International Business Machines CorporationInventors: John Knickerbocker, Bing Dang, Qianwen Chen, Joshua M. Rubin, Arvind Kumar
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Publication number: 20230178404Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.Type: ApplicationFiled: December 3, 2021Publication date: June 8, 2023Inventors: Akihiro Horibe, Qianwen Chen, RISA MIYAZAWA, Michael P. Belyansky, John Knickerbocker, Takashi Hisada
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Publication number: 20230100769Abstract: An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: John Knickerbocker, Mukta Ghate Farooq, Katsuyuki Sakuma
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Publication number: 20230098054Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Lei Shan, Daniel Joseph Friedman, Griselda Bonilla, John Knickerbocker
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Publication number: 20230087366Abstract: A carrier wafer, a structure, and a method are disclosed. The carrier wafer includes a wafer layer having a first surface and a second surface opposite the first surface, a first antireflective coating (ARC) layer positioned on the first surface of the wafer layer, a second ARC layer positioned on a surface of the first ARC layer opposite the wafer layer, and a thin release layer positioned on a surface of the second ARC layer opposite the first ARC layer. The structure includes the carrier wafer and a semiconductor device substrate positioned over the thin release layer of the carrier wafer. The method includes obtaining a wafer layer, forming an ARC layer on a surface of the wafer layer, forming a second ARC layer on a surface of the first ARC layer opposite the wafer layer, and forming a thin release layer on the second ARC layer.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Inventors: Qianwen Chen, Michael P. Belyansky, John Knickerbocker, Akihiro Horibe
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Patent number: 11587860Abstract: Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.Type: GrantFiled: March 8, 2020Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: John Knickerbocker, Bing Dang, Raymond Horton, Joana Maria
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Patent number: 11539088Abstract: Microbatteries and methods for forming microbatteries are provided. The microbatteries and methods address at least one or both of edge sealing issues for edges of a stack forming part of a microbatteries and overall sealing for individual cells for microbatteries in a batch process. A transferable solder molding apparatus and sealing structure are proposed in an example to provide a metal casing for a solid-state thin-film microbattery. An exemplary proposed process involves deposition or pre-forming low-temperature solder casing separately from the microbatteries. Then a thermal compression may be used to transfer the solder casing to each battery cell, with a handler apparatus in a batch process in an example. These exemplary embodiments can address the temperature tolerance constrain for solid state thin film battery during handling, metal sealing, and packaging.Type: GrantFiled: March 9, 2020Date of Patent: December 27, 2022Assignee: International Business Machines CorporationInventors: Bing Dang, Leanna Pancoast, Jae-Woong Nah, John Knickerbocker
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Patent number: 11522243Abstract: A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.Type: GrantFiled: December 21, 2020Date of Patent: December 6, 2022Assignee: International Business Machines CorporationInventors: Qianwen Chen, Jae-Woong Nah, Bing Dang, Leanna Pancoast, John Knickerbocker
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Publication number: 20220200086Abstract: A method of manufacturing a micro-battery is provided. The method includes forming a micro-battery device by forming a first metal anode via and a first metal cathode via in a first substrate, forming a first metal layer on a bottom side of the first substrate, forming a first battery element on a top side of the substrate, forming an encapsulation layer around the first battery element, forming trenches through the encapsulation layer and the first substrate on different sides of the first battery element, and forming a metal sealing layer in the trenches to cover at least a plurality of sidewall surfaces of the first battery element. The metal sealing layer is electrically connected to the battery element through the first metal layer and the first metal cathode via.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Qianwen Chen, Jae-Woong Nah, Bing Dang, Leanna Pancoast, John Knickerbocker
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Publication number: 20220199235Abstract: A mechanism is provided in a data processing system to implement a multi-sensor health monitoring platform. The mechanism applies a machine learning model to predict patient needs and patient activity trends based on physiological features and activity features of the patient. The mechanism applies the machine learning model to predict energy requirements for a plurality of medical sensors based on the predicted patient needs and patient activity trends. The mechanism schedules recharging of the plurality of medical sensors based on the predicted energy requirements and identifying one or more sensors to set to an activate state based on the predicted patient needs and patient activity trends. The mechanism collecting sensor data from the one or more sensors and applies the machine learning model to generate a point-of-care recommendation based on the collected sensor data.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: John Knickerbocker, Bing Dang, Qianwen Chen, Leanna Pancoast
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Patent number: 11315902Abstract: Multi-semiconductor chip modules that have a substrate with a substrate surface, one or more first substrate connections, and one or more second substrate connections. One or more first semiconductor chips (chips) has one or more larger first chip connections and one or more smaller first chip connections on a first chip bottom surface. One or more of the larger first chip connections physically and electrically connected to a respective first substrate connection. One or more second chips has one or more larger second chip connections and one or more smaller second chip connections on a second chip bottom surface. One or more of the larger second chip connections physically and electrically connected to a respective second substrate connection. A bridge has a bridge thickness, a bridge surface, and one or more bridge connections on the bridge surface. A first part of the bridge surface is under the first chip bottom surface and a second part of the bridge surface is under the second chip bottom surface.Type: GrantFiled: February 12, 2020Date of Patent: April 26, 2022Assignee: International Business Machines CorporationInventor: John Knickerbocker
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Patent number: 11307147Abstract: Techniques for colorimetric based test strip analysis and reader system are provided. In one aspect, a method of test strip analysis includes: illuminating a test strip wetted with a sample with select spectrums of light, wherein the test strip includes test pads that are configured to change color in the presence of an analyte in the sample; obtaining at least one digital image of the test strip; and analyzing color intensity from the at least one digital image against calibration curves to determine an analyte concentration in the sample with correction for one or more interference substances in the sample that affect the color intensity. A calibration method and a reader device are also provided.Type: GrantFiled: February 20, 2020Date of Patent: April 19, 2022Assignee: International Business Machines CorporationInventors: Minhua Lu, Vince Siu, Russell Budd, Evan Colgan, John Knickerbocker
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Patent number: 11222862Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.Type: GrantFiled: October 21, 2019Date of Patent: January 11, 2022Assignee: International Business Machines CorporationInventors: Qianwen Chen, Bing Dang, Russell Budd, Bo Wen, Li-Wen Hung, Jae-Woong Nah, John Knickerbocker
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Publication number: 20210366789Abstract: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.Type: ApplicationFiled: May 25, 2020Publication date: November 25, 2021Inventors: John Knickerbocker, Bing Dang, Qianwen Chen, Joshua M. Rubin, Arvind Kumar
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Patent number: 11171374Abstract: Systems and/or techniques associated with a solid-state microbattery packaging system are provided. In one example, a device comprises a substrate layer and a tape substrate layer. The substrate layer is associated with a set of solid-state microbattery components. The tape substrate comprises a releasable adhesive material and a polymer sealing material. A conductive surface associated with the set of solid-state microbattery components is disposed on the releasable adhesive material of the tape substrate layer.Type: GrantFiled: December 14, 2017Date of Patent: November 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qianwen Chen, Bing Dang, John Knickerbocker, Bo Wen
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Publication number: 20210280834Abstract: Microbatteries and methods for forming microbatteries are provided. The microbatteries and methods address at least one or both of edge sealing issues for edges of a stack forming part of a microbatteries and overall sealing for individual cells for microbatteries in a batch process. A transferable solder molding apparatus and sealing structure are proposed in an example to provide a metal casing for a solid-state thin-film microbattery. An exemplary proposed process involves deposition or pre-forming low-temperature solder casing separately from the microbatteries. Then a thermal compression may be used to transfer the solder casing to each battery cell, with a handler apparatus in a batch process in an example. These exemplary embodiments can address the temperature tolerance constrain for solid state thin film battery during handling, metal sealing, and packaging.Type: ApplicationFiled: March 9, 2020Publication date: September 9, 2021Inventors: Bing Dang, Leanna Pancoast, Jae-Woong Nah, John Knickerbocker
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Publication number: 20210265606Abstract: Thin Film Batteries are made of battery layers. Each battery layer has a substrate with one or more battery structures on the substrate surface. The battery structures have a first electrode connection and a second electrode, a first electrode (e.g. a cathode or anode) is electrically connected to the first electrode connection and a second electrode (e.g. an anode or cathode) is electrically connected to the second electrode connection. An electrolyte is at least partial disposed between and electrically connected to the first and second electrodes. A first edge connection on one of the substrate edges is physically and electrically connected to the first electrode connection. A second edge connection on one of the substrate edges is physically and electrically connected to the second electrode connection. An electrically insulating lamination is disposed on the substrate and covers the components except for the first and second edge connections, connected to respective battery electrodes.Type: ApplicationFiled: February 20, 2020Publication date: August 26, 2021Inventors: Bing Dang, John Knickerbocker, Qianwen Chen
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Patent number: 11101513Abstract: Techniques regarding a thin film battery, which can comprise one or more sealing layers, and a method of manufacturing thereof are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a thin film battery cell encapsulated in a multi-layer stack comprising an adhesive layer located between a first substrate layer and a second substrate layer. The apparatus can also comprise a metal sealing layer at least partially surrounding the multi-layer stack.Type: GrantFiled: September 4, 2018Date of Patent: August 24, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qianwen Chen, Bing Dang, Bo Wen, Marlon Agno, John Knickerbocker
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Patent number: 11094407Abstract: A drug delivery form includes a drug and electronics. The electronics includes memory(ies) having drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The electronics includes communication circuitry configured to read data from and write data to the drug delivery form information. An apparatus includes memory(ies) having computer readable code, and processor(s). The processor(s) cause the apparatus to perform operations including communicating with a drug delivery form including a drug and drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The processor(s) cause the apparatus to perform reading data from or writing data into the drug and drug delivery form information.Type: GrantFiled: June 13, 2019Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: John Knickerbocker, Li-Wen Hung, Bing Dang, Katsuyuki Sakuma, Jeffrey Donald Gelorme, Rajeev Narayanan, Qianwen Chen
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Publication number: 20210249381Abstract: Multi-semiconductor chip modules that have a substrate with a substrate surface, one or more first substrate connections, and one or more second substrate connections. One or more first semiconductor chips (chips) has one or more larger first chip connections and one or more smaller first chip connections on a first chip bottom surface. One or more of the larger first chip connections physically and electrically connected to a respective first substrate connection. One or more second chips has one or more larger second chip connections and one or more smaller second chip connections on a second chip bottom surface. One or more of the larger second chip connections physically and electrically connected to a respective second substrate connection. A bridge has a bridge thickness, a bridge surface, and one or more bridge connections on the bridge surface. A first part of the bridge surface is under the first chip bottom surface and a second part of the bridge surface is under the second chip bottom surface.Type: ApplicationFiled: February 12, 2020Publication date: August 12, 2021Inventor: John Knickerbocker