Abstract: Disclosed systems and techniques are directed to efficient integrity monitoring of computational operations using multiple memory arrays collectively representative of known events associated with the computational operations. Disclosed techniques include obtaining event identification value representative of a state of the computing device associated with execution of an operation on the computing device, obtaining memory pointers and selecting, based on the memory pointers, mapping values from multiple memory arrays, computing an event response value, and classifying the operation among a plurality of classes, based on the event response value.

Abstract: A DMA system includes two or more DMA engines that facilitate transfers of data through a shared memory. The DMA engines may operate independently of each other and with different throughputs. A data flow control module controls data flow through the shared memory by tracking status information of data blocks in the shared memory. The data flow control module updates the status information in response to read and write operations to indicate whether each block includes valid data that has not yet been read or if the block has been read and is available for writing. The data flow control module shares the status information with the DMA engines via a side-channel interface to enable the DMA engines to determine which block to write to or read from.

Abstract: Multiple helper data solutions (a.k.a., helper data images) are generated to produce preselected non-random values (a.k.a., “target values”) from a physically unclonable function (PUF) circuit. Therefore, multiple preselected PUF output values may be generated for a given integrated circuit die, where each the output values are derived from a combination of the chip-unique PUF circuit and the chip-unique helper data solution. These helper data blocks are stored in a nonvolatile memory on the integrated circuit die. In an embodiment, the preselected non-random values may be used as secret encryption or decryption keys. In this manner, multiple secret values can be reliably stored within a chip, using a combination of the chip-unique PUF circuit and the multiple chip-unique helper data solution.

Abstract: A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.

Abstract: The present invention discloses a detection apparatus, comprising a base layer, wherein the base layer comprises a groove for containing a testing element and a sample chamber for collecting a fluid sample. The detection apparatus can achieve fast, efficient and accurate detection of analytes in liquid samples, make operators to perform testing conveniently and freely, without causing incorrect results. In some preferred modes, the sample chamber comprises a liquid channel.

Abstract: A request to perform a memory operation addressed to a first address corresponding to a first logical unit of logical units of a memory is received. Address mask data that corresponds to the logical units is identified. Multiple transformed addresses are determined using the first address and the address mask data. The transformed addresses can include a target address corresponding to the first logical unit and additional addresses corresponding to other logical units. The memory operation is performed at the target address corresponding to the first logical unit and dummy memory operations are performed at the additional addresses corresponding to the additional logical units.

Abstract: A value corresponding to a physical variation of a device may be received. Furthermore, helper data associated with the physical variation of the device may be received. A result data may be generated based on a combination of the value corresponding to the physical variation of the device and the helper data. An error correction operation may be performed on the result data to identify one or more code words associated with the error correction operation. Subsequently, a target data may be generated based on the one or more code words.

Abstract: Technologies for protecting a secure context in a hardware root of trust (ROT) are described. One hardware ROT includes key generation logic and a cryptographic circuit. The key generation logic generates a first key from a value, corresponding to a physical variation of the hardware ROT, and first helper data associated with the physical variation of the hardware ROT. The key generation logic generates a second key from the value and second helper data associated with the physical variation of the hardware ROT. The cryptographic circuit receives a first encrypted secure context from off-chip storage and decrypts the first encrypted secure context using the first key to obtain a secure context. The cryptographic circuit encrypts the secure context using the second key to obtain a second encrypted secure context and stores the second encrypted secure context in the off-chip storage.

Abstract: The present invention discloses a detection apparatus, comprising a base layer, wherein the base layer comprises a groove for containing a testing element and a sample chamber for collecting a fluid sample. The detection apparatus can achieve fast, efficient and accurate detection of analytes in liquid samples, make operators to perform testing conveniently and freely, without causing incorrect results. In some preferred modes, the sample chamber comprises a liquid channel.

Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to: receive a request to perform a management operation on a target information handling system, wherein the request is received from a mobile device via a mobile network, and wherein the request includes data retrieved from a visual identifier associated with the target information handling system; and perform the management operation by communicating with the target information handling system via a management network other than the mobile network.

Abstract: Embodiments for a networking device are disclosed. The networking device includes a private identity-based cryptographic (IBC) key issued for a first device. The networking device can receive an internet protocol (IP) packet from the first device. The networking device modifies the IP packet to form a modified IP packet, wherein modify the IP packet includes add an extension header to the IP packet. The extension header includes a source identifier identifying the first device, an indication of the key generation authority and an indication of an identity-based encryption (IBE) algorithm. The networking device also generates an identity-based signature (IBS) using the IBC algorithm with the source identifier as an identity input, the modified IP packet as a message input, and the private IBC key for the first device as a private key input. The modified IP packet and the IBS is then sent towards a destination of the IP packet.

Abstract: Embodiments of the disclosure provide a system for analyzing noise data for light detection and ranging (LiDAR). The system includes a communication interface configured to sequentially receive noise data of the LiDAR in time windows, at least one storage device configured to store instructions, and at least one processor configured to execute the instructions to perform operations. Exemplary operations include determining an estimated noise value of a first time window using the noise data received in the first time window and determining an instant noise value of a second time window using the noise data received in the second time window. The second time window is immediately subsequent to the first time window. The operations also include determining an estimated noise value of the second time window by aggregating the estimated noise value of the first time window and the instant noise value of the second time window.

Abstract: A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.

Abstract: A screen repair patch and a screen flaw repair method. The screen repair patch includes an optical layer, a substrate layer, and an adhesion layer. The optical layer and a screen to be repaired have the same or similar optical performance. The substrate layer has a thickness of 10 to 250 microns. The adhesion layer has a thickness of 5 to 200 microns. In the screen flaw repair method, a repair patch is cut off from a region on a patch sheet corresponding to the position of a flaw of a screen, and the repair patch is attached to the corresponding position of the flaw of the screen by using a joining direction of the screen as an affixing direction of the repair patch.

Abstract: A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.