Patents by Inventor Jonathan D. Reid
Jonathan D. Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120175263Abstract: Methods, systems, and apparatus for plating a metal onto a work piece with a plating solution having a low oxygen concentration are described. In one aspect, a method includes reducing an oxygen concentration of a plating solution. The plating solution includes about 100 parts per million or less of an accelerator. After reducing the oxygen concentration of the plating solution, a wafer substrate is contacted with the plating solution in a plating cell. The oxygen concentration of the plating solution in the plating cell is about 1 part per million or less. A metal is electroplated with the plating solution onto the wafer substrate in the plating cell. After electroplating the metal onto the wafer substrate, an oxidizing strength of the plating solution is increased.Type: ApplicationFiled: December 13, 2011Publication date: July 12, 2012Inventors: Kousik GANESAN, Tighe SPURLIN, Jonathan D. REID, Shantinath GHONGADI, Andrew McKERROW, James E. DUNCAN
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Patent number: 8197662Abstract: The present invention provides improved methods and devices for electroplating copper on a wafer. Some implementations of the present invention involve the pre-treatment of the wafer with a solution containing accelerator molecules. Preferably, the bath into which the wafer is subsequently placed for electroplating has a reduced concentration of accelerator molecules. The pre-treatment causes a reduction in roughness of the electroplated copper surface, particularly during the initial phases of copper growth.Type: GrantFiled: December 17, 2010Date of Patent: June 12, 2012Assignee: Novellus Systems, Inc.Inventors: Eric Webb, Jonathan D. Reid, Yuichi Takada, Timothy Archer
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Patent number: 8172992Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.Type: GrantFiled: December 8, 2009Date of Patent: May 8, 2012Assignee: Novellus Systems, Inc.Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida
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Patent number: 8147660Abstract: A semiconductive counter electrode covers a highly electronically conductive electric current buss. The semiconductive counter electrode is impervious to ion flow. A substrate holder is operable to hold a substrate and to form a thin fluid gap between the semiconductive counter electrode and a substrate surface. A thin liquid electrolyte layer is located in the thin fluid gap. A power supply connected to the electric current buss and a peripheral edge of a conductive substrate surface is able to generate a potential difference between the electric current buss and the semiconductive counter electrode, on one side of the electrolyte layer, and the substrate on the other side. The semiconductive counter electrode provides a substantial resistance in the various current flow paths between the electric current buss and the semiconductive counter electrode, on one side, and the conductive substrate surface, on the other, thereby enhancing control of current distribution.Type: GrantFiled: March 30, 2007Date of Patent: April 3, 2012Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Jonathan D. Reid
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Publication number: 20120031768Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.Type: ApplicationFiled: October 11, 2011Publication date: February 9, 2012Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Wiley
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Patent number: 8043958Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: September 3, 2010Date of Patent: October 25, 2011Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 8043967Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.Type: GrantFiled: April 16, 2010Date of Patent: October 25, 2011Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Wiley
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Patent number: 7967969Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.Type: GrantFiled: October 13, 2009Date of Patent: June 28, 2011Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Jonathan D. Reid
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Publication number: 20110083965Abstract: An electroplating apparatus for filling recessed features on a semiconductor substrate includes an electrolyte concentrator configured for concentrating an electrolyte having Cu2+ ions to form a concentrated electrolyte solution that would have been supersaturated at 20° C. The electrolyte is maintained at a temperature that is higher than 20° C., such as at least at about 40° C. The apparatus further includes a concentrated electrolyte reservoir and a plating cell, where the plating cell is configured for electroplating with concentrated electrolyte at a temperature of at least about 40° C. Electroplating with electrolytes having Cu2+ concentration of at least about 60 g/L at temperatures of at least about 40° C. results in very fast copper deposition rates, and is particularly well-suited for filling large, high aspect ratio features, such as through-silicon vias.Type: ApplicationFiled: October 12, 2009Publication date: April 14, 2011Applicant: NOVELLUS SYSTEMS, INC.Inventors: Jonathan D. Reid, Seshasayee Varadarajan, Steven T. Mayer
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Patent number: 7897198Abstract: Electroless plating is performed to deposit conductive materials on work pieces such as partially fabricated integrated circuits. Components of an electroless plating bath are separately applied to a work piece by spin coating to produce a very thin conductive layer (in the range of a few hundred angstroms). The components are typically a reducing agent and a metal source.Type: GrantFiled: September 3, 2002Date of Patent: March 1, 2011Assignee: Novellus Systems, Inc.Inventors: Heung L. Park, Eric G. Webb, Jonathan D. Reid, Timothy Patrick Cleary
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Patent number: 7811925Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: July 31, 2008Date of Patent: October 12, 2010Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 7776741Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.Type: GrantFiled: August 18, 2008Date of Patent: August 17, 2010Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
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Publication number: 20100200412Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.Type: ApplicationFiled: April 16, 2010Publication date: August 12, 2010Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Wiley
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Publication number: 20100155254Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.Type: ApplicationFiled: December 8, 2009Publication date: June 24, 2010Inventors: Vinay Prabhakar, Bryan L. Buckalew, Kousik Ganesan, Shantinath Ghongadi, Zhian He, Steven T. Mayer, Robert Rash, Jonathan D. Reid, Yuichi Takada, James R. Zibrida
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Patent number: 7727863Abstract: Sonic radiation is applied to a wafer portion of the planar surface of a rotating, tilted wafer as it is being immersed into a liquid treatment bath. The portion includes the leading outer edge region of the wafer. The area of the wafer portion is significantly less than the total surface area of the planar wafer surface. Power density is minimized. As a result, bubbles are removed from the wafer surface and cavitation in the liquid bath is avoided. In some embodiments, the liquid bath is de-gassed to inhibit bubble formation.Type: GrantFiled: September 29, 2008Date of Patent: June 1, 2010Assignee: Novellus Systems, Inc.Inventors: Bryan L. Buckalew, Jonathan D. Reid, Johanes H. Sukamto, Frederick Dean Wilmot, Richard S. Hill
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Patent number: 7686927Abstract: The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.Type: GrantFiled: August 25, 2006Date of Patent: March 30, 2010Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Steven T. Mayer, Seshasayee Varadarajan, David C. Smith, Evan E. Patton, Dinesh S. Kalakkad, Gary Lind, Richard S. Hill
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Publication number: 20100041226Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. Low copper concentration and high acidity electroplating solution is used for deposition copper into the through silicon vias.Type: ApplicationFiled: August 18, 2008Publication date: February 18, 2010Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
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Publication number: 20100032304Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.Type: ApplicationFiled: October 13, 2009Publication date: February 11, 2010Applicant: NOVELLUS SYSTEMS, INC.Inventors: Steven T. Mayer, Jonathan D. Reid
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Patent number: 7622024Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.Type: GrantFiled: January 20, 2005Date of Patent: November 24, 2009Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Jonathan D. Reid
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Patent number: 7605082Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: October 13, 2005Date of Patent: October 20, 2009Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer