Patents by Inventor Jong-bum Park

Jong-bum Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240148977
    Abstract: A drug administration management system according to an embodiment of the present disclosure may include a smart case configured to accommodate a drug administration device, display drug administration information including whether or not a drug is administered and a drug administration dose for each drug administration site input button based on an input of a user, and transmit the drug administration information externally; and a terminal configured to receive the externally transmitted drug administration information from the smart case, and monitor the drug administration information based on a drug administration plan input from a user.
    Type: Application
    Filed: March 8, 2022
    Publication date: May 9, 2024
    Inventors: Jong Won Lim, Hye Won LEE, Hyoung Seok KIM, Soo Bum PARK, Sang Hoon OH
  • Publication number: 20240136763
    Abstract: A plug connector according to an embodiment of the present disclosure, wherein the housing of the plug connector includes a mating portion extending forward and a latching portion equipped in the housing. The latching portion may include, as a root having a lower end connected to the upper surface of the housing, a root extending to the upper end with the lower end of the route as a first fulcrum to form a cantilever structure; and as a pair of latching arms having a rear end connected to an upper end of the root, a pair of latching arms extending to the front end with the upper end of the root as a second fulcrum to form a pair of hooks. Each front end of the pair of latching arms may include an outward protrusion.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Inventors: Sa Cheol Hong, Jong Deok Park, Jang Bum Jin
  • Publication number: 20240072492
    Abstract: An electrical connector according to a disclosed embodiment includes a housing having a terminal receiving opening, and a TPA member mounted outside the terminal receiving opening to fix a position of a terminal. The TPA member includes first and second side cantilever arms which are extended from both ends of the TPA member, respectively, and are positioned outside a sidewall of the housing, the housing is not in contact with the TPA member in a preliminary mounting position, and the housing is latch-coupled with the first and second side cantilever arms in a final mounting position.
    Type: Application
    Filed: January 27, 2022
    Publication date: February 29, 2024
    Inventors: Jang Bum Jin, Jong Deok Park, Sa Cheol Hong
  • Patent number: 11581024
    Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: February 14, 2023
    Assignee: SK hynix Inc.
    Inventors: Sang Kug Lym, Jong Bum Park, Kyoung Lae Cho
  • Publication number: 20220139428
    Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.
    Type: Application
    Filed: January 12, 2022
    Publication date: May 5, 2022
    Applicant: SK hynix Inc.
    Inventors: Sang Kug LYM, Jong Bum PARK, Kyoung Lae CHO
  • Publication number: 20220139427
    Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.
    Type: Application
    Filed: January 12, 2022
    Publication date: May 5, 2022
    Applicant: SK hynix Inc.
    Inventors: Sang Kug LYM, Jong Bum PARK, Kyoung Lae CHO
  • Patent number: 11322501
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 11257527
    Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Kug Lym, Jong Bum Park, Kyoung Lae Cho
  • Patent number: 11217592
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 11056153
    Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Sang Kug Lym, Jong Bum Park
  • Publication number: 20200335505
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Publication number: 20200279588
    Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: SK hynix Inc.
    Inventors: Sang Kug LYM, Jong Bum PARK, Kyoung Lae CHO
  • Patent number: 10734389
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20200152637
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10580777
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20200043933
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 6, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Publication number: 20190392870
    Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.
    Type: Application
    Filed: September 4, 2019
    Publication date: December 26, 2019
    Applicant: SK hynix Inc.
    Inventors: Sang Kug LYM, Jong Bum PARK
  • Publication number: 20190353629
    Abstract: Provided is a gas detection apparatus including: a main body in which a gas sensor is mounted; an inlet part disposed under the main body to introduce a gas present in a detection space; and a plurality of inlet holes formed to pass through the inlet part, wherein, in each of the inlet holes, an area of an inlet facing the detection space is greater than that of an outlet facing the main body.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 21, 2019
    Inventors: Yeon Kyu JUNG, Jae Ho YOO, Seung Wook CHOI, Jong Bum PARK, Taek Heon AHN
  • Patent number: 10483265
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 10446194
    Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang Kug Lym, Jong Bum Park