Patents by Inventor Jong Chern Lee
Jong Chern Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7733162Abstract: A pumping voltage generating circuit of a semiconductor memory apparatus, the pumping voltage generating circuit includes a detecting unit configured to compare a level of a pumping voltage with a level of a reference voltage to generate a detection signal, an oscillating signal generator configured to sequentially generate a first oscillating signal and a second oscillating signal in response to the detection signal, and to elevate frequencies of the first and second oscillating signals when the second oscillating signal is generated, a first pump configured to perform a pumping operation in response to the first oscillating signal, and a second pump configured to perform a pumping operation in response to the second oscillating signal, wherein output terminals of the first pump and the second pump are commonly connected, and the pumping voltage is output at the output terminals of the first pump and the second pump.Type: GrantFiled: December 3, 2008Date of Patent: June 8, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jong-Sam Kim, Jong-Chern Lee
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Patent number: 7705636Abstract: The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.Type: GrantFiled: December 26, 2007Date of Patent: April 27, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Je Yoon Kim, Jong Chern Lee
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Patent number: 7622962Abstract: A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.Type: GrantFiled: July 19, 2007Date of Patent: November 24, 2009Assignee: Hynix Semiconductor Inc.Inventors: Dae-Suk Kim, Jong Chern Lee
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Publication number: 20090231022Abstract: A pumping voltage generating circuit of a semiconductor memory apparatus, the pumping voltage generating circuit includes a detecting unit configured to compare a level of a pumping voltage with a level of a reference voltage to generate a detection signal, an oscillating signal generator configured to sequentially generate a first oscillating signal and a second oscillating signal in response to the detection signal, and to elevate frequencies of the first and second oscillating signals when the second oscillating signal is generated, a first pump configured to perform a pumping operation in response to the first oscillating signal, and a second pump configured to perform a pumping operation in response to the second oscillating signal, wherein output terminals of the first pump and the second pump are commonly connected, and the pumping voltage is output at the output terminals of the first pump and the second pump.Type: ApplicationFiled: December 3, 2008Publication date: September 17, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Jong Sam Kim, Jong Chern Lee
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Publication number: 20090167417Abstract: A charge pumping circuit consumes less current by reducing the number of charge pumps operating simultaneously. The charge pumping circuit includes a voltage sensor that detects a level of a high voltage and outputs a control signal based on the detection result. An oscillator provides an oscillating clock signal in response to the control signal of the voltage sensor, and the oscillator sequentially outputs the clock signal as a plurality of clock signals having shifted phases A plurality of high-voltage pumps are disposed in a plurality of regions to pump the high voltage in response to the clock signals and a different phase is designated for each region.Type: ApplicationFiled: June 10, 2008Publication date: July 2, 2009Inventors: Jong Sam KIM, Jong Chern LEE
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Publication number: 20090146697Abstract: The buffer circuit includes a differential amplifier differentially amplifying a reference node corresponding to a reference voltage and an input node corresponding to the input signal by sensing a potential difference of the reference voltage and the input signal. A coupling unit couples the input signal to the reference node, making it possible to improve the operating speed of the buffer circuit and operate normally when a level of the input signal or the reference voltage becomes low.Type: ApplicationFiled: June 11, 2008Publication date: June 11, 2009Inventor: Jong Chern LEE
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Patent number: 7539064Abstract: A precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first core voltage to a pair of local input/output lines, in response to a first precharge signal, to precharge the pair of local input/output lines. The second precharge unit applies a clamp voltage, which is generated using a first supply voltage, to the pair of local input/output lines, in response to the first precharge signal, to precharge the pair of local input/output lines.Type: GrantFiled: December 20, 2006Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventor: Jong Chern Lee
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Publication number: 20090066371Abstract: The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.Type: ApplicationFiled: December 26, 2007Publication date: March 12, 2009Inventors: Je Yoon KIM, Jong Chern LEE
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Patent number: 7492646Abstract: An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.Type: GrantFiled: March 14, 2007Date of Patent: February 17, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jong-Chern Lee, Sun-Hye Shin
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Publication number: 20080136484Abstract: A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.Type: ApplicationFiled: July 19, 2007Publication date: June 12, 2008Applicant: Hynix Semiconductor Inc.Inventors: Dae-Suk Kim, Jong Chern Lee
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Patent number: 7339851Abstract: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.Type: GrantFiled: January 2, 2007Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventor: Jong Chern Lee
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Patent number: 7339397Abstract: A data output apparatus and method in a global input and output (GIO) line transmits data via the GIO line. This data output apparatus includes a read driver driven responsive to an input of read data for inverting and amplifying the data to output inverted and amplified data onto the GIO line, a GIO termination unit driven responsive to a termination signal for rising or falling a voltage level on the GIO line by a preset level, prior to driving the data onto the GIO line by the read driver, and a receiver driven responsive to the read data transmitted through the GIO line for inverting and amplifying the read data to provide inverted and amplified data. This data output apparatus can enable a high rate data transmission by decreasing a swing width of data transmitted via the GIO line and also reduce a coupling noise on adjacent lines.Type: GrantFiled: July 8, 2005Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventor: Jong-Chern Lee
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Patent number: 7317338Abstract: The present invention provides an input buffer for use in a semiconductor device reducing a current consumption and maintaining a reliable operation speed by detecting a level of the reference voltage. The input buffer includes a comparator, having a first biasing device controlled by a buffer enable signal, for sensing a logic level of an input data by comparing voltage levels of a reference voltage and the input data, a reference voltage detector for detecting the level of the reference voltage, and a second biasing device controlled by an output signal from the reference voltage detector and parallel connected to the first biasing device.Type: GrantFiled: July 15, 2005Date of Patent: January 8, 2008Assignee: Hynix Semiconductor Inc.Inventor: Jong-Chern Lee
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Publication number: 20080001582Abstract: An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.Type: ApplicationFiled: March 14, 2007Publication date: January 3, 2008Inventors: Jong-Chern Lee, Sun-Hye Shin
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Publication number: 20070263465Abstract: Disclosed is a precharge circuit of a semiconductor apparatus. The precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first core voltage to a pair of local input/output lines, in response to a first precharge signal, to precharge the pair of local input/output lines. The second precharge unit applies a clamp voltage, which is generated using a first supply voltage, to the pair of local input/output lines, in response to the first precharge signal, to precharge the pair of local input/output lines.Type: ApplicationFiled: December 20, 2006Publication date: November 15, 2007Applicant: Hynix Semiconductor Inc.Inventor: Jong Chern Lee
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Patent number: 7177226Abstract: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.Type: GrantFiled: May 11, 2005Date of Patent: February 13, 2007Assignee: Hynix Semiconductor Inc.Inventor: Jong Chern Lee
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Patent number: 7157893Abstract: There is provided a reference voltage generator that generates a constant reference voltage regardless of a change in temperature. The reference voltage generator includes a temperature-compensated current generating part for reducing a supply current provided to an output terminal in response to an increase of temperature, and a diode for receiving the supply current through the output terminal.Type: GrantFiled: June 29, 2004Date of Patent: January 2, 2007Assignee: Hynix Semiconductor Inc.Inventor: Jong-Chern Lee
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Publication number: 20060221717Abstract: A data output apparatus and method in a global input and output (GIO) line transmits data via the GIO line. This data output apparatus includes a read driver driven responsive to an input of read data for inverting and amplifying the data to output inverted and amplified data onto the GIO line, a GIO termination unit driven responsive to a termination signal for rising or falling a voltage level on the GIO line by a preset level, prior to driving the data onto the GIO line by the read driver, and a receiver driven responsive to the read data transmitted through the GIO line for inverting and amplifying the read data to provide inverted and amplified data. This data output apparatus can enable a high rate data transmission by decreasing a swing width of data transmitted via the GIO line and also reduce a coupling noise on adjacent lines.Type: ApplicationFiled: July 8, 2005Publication date: October 5, 2006Inventor: Jong-Chern Lee
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Publication number: 20060208762Abstract: The present invention provides an input buffer for use in a semiconductor device reducing a current consumption and maintaining a reliable operation speed by detecting a level of the reference voltage. The input buffer includes a comparator, having a first biasing device controlled by a buffer enable signal, for sensing a logic level of an input data by comparing voltage levels of a reference voltage and the input data, a reference voltage detector for detecting the level of the reference voltage, and a second biasing device controlled by an output signal from the reference voltage detector and parallel connected to the first biasing device.Type: ApplicationFiled: July 15, 2005Publication date: September 21, 2006Inventor: Jong-Chern Lee
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Patent number: 6998901Abstract: Provided is a self refresh oscillator which includes a plurality of inverters serially connected between an input terminal and an output terminal; a pull up driver for charging a first node in accordance with a level of the output terminal; a comparator for comparing a potential of the first node with a reference voltage and outputting the result to the input terminal; and a period adjusting unit for operating based on a level of the output terminal and adjusting an amount of current discharged into a ground of the first node in accordance with a temperature.Type: GrantFiled: June 29, 2004Date of Patent: February 14, 2006Assignee: Hynix Semiconductor Inc.Inventor: Jong Chern Lee