Abstract: Provided are a biosensor using a silicon nanowire and a method of manufacturing the same. The silicon nanowire can be formed to have a shape, in which identical patterns are continuously repeated, to enlarge an area in which probe molecules are fixed to the silicon nanowire, thereby increasing detection sensitivity. In addition, the detection sensitivity can be easily adjusted by adjusting a gap between the identical patterns of the silicon nanowire depending on characteristics of target molecules, without adjusting a line width of the silicon nanowire in the conventional art. Further, the gap between the identical patterns of the silicon nanowire can be adjusted depending on characteristics of the target molecule to differentiate detection sensitivities, thereby simultaneously detecting various detection sensitivities.

Abstract: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.

Abstract: A silicon light emitting diode capable of effectively utilizing light radiated toward the lateral side of a substrate by including a side reflecting mirror is provided. The silicon-based light emitting diode includes a p-type silicon substrate having a plurality of grooves, a light emitting diode layer formed on each of the grooves of the silicon substrate, the light emitting diode layer including an active layer, an n-type doped layer, and a transparent electrode layer, and a metal electrode including a lower metal electrode formed on the bottom surface of the p-type silicon substrate and an upper metal electrode formed on the top surface of the transparent electrode layer. The lateral surface of each of the grooves is separated from the light emitting diode layer and used as a reflecting mirror The lateral surface is referred to as the side reflecting mirror.

Abstract: Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode.

Abstract: Provided is a method of manufacturing a nano size-gap electrode device. The method includes the steps of: disposing a floated nano structure on a semiconductor layer; forming a mask layer having at least one opening pattern to intersect the nano structure; and depositing a metal on the semiconductor layer exposed through the opening pattern to form an electrode, such that a nano size-gap is provided under the nano structure by the nano structure.

Abstract: Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.

Abstract: Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

Abstract: Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

Abstract: Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

Abstract: Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused.

Abstract: Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused.

Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided.

Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided.