Abstract: Disclosed herein are a lamp module that includes a double insulation structure and a cooling structure, thus being usable even in a high temperature condition, and a cooking appliance including the same. The cooking appliance includes a cooking compartment, a cooling fan disposed at an upper portion of the cooking compartment to suction outside air, and a lamp module configured to illuminate an inside of the cooking compartment and disposed adjacent to the cooling fan to exchange heat with the outside air suctioned by the cooling fan.

Abstract: Disclosed herein is a cooking appliance having an improved cooling mechanism. The cooking appliance includes a first cavity forming a first cooking chamber and a second cavity forming a second cooking chamber, and has a cooling mechanism for cooling both the first cavity and the second cavity. A separate third cooling channel is formed to exhaust air from the first cooking chamber. A vent for the first and second cavities may be formed at a lower portion of the second cavity such that air may be exhausted via the vent.

Abstract: Disclosed is a method for detecting a cyberthreat through correlation analysis of security events, which includes extracting a false-positive data set by extracting, from source data, information about security events occurring during a predetermined time period based on a time at which erroneous detection occurred; extracting a true-positive data set by extracting, from the source data, information about security events occurring during the predetermined time period based on a time at which an intrusion threat was correctly detected; extracting a current data set by extracting information about security events occurring during the predetermined time period from data to be analyzed; generating event coincidence statistics by extracting a frequency of each security event in the respective data sets and by compiling statistics thereon; generating an event vector based on the event coincidence statistics; and performing intrusion threat detection through a vector space model based on the event vector.

Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells coupled to a plurality of bit lines and a page buffer circuit coupled to the plurality of bit lines and including a plurality of page buffers, wherein the plurality of page buffers sense program states of the plurality of memory cells through the plurality of bit lines during a verify operation or a read operation of a program operation, and wherein the plurality of page buffers perform in an alternate way a latch operation for latching sensing data in accordance with current amounts of the plurality of bit lines.

Abstract: A wireless power receiver is disclosed. The wireless power receiver comprises: a resonance tank for receiving magnetic resonance-type wireless power; a rectifier including a diode bridge and a first switch connected to both ends of any one diode for forming the diode bridge, so as to rectify wireless power received by the resonance tank and supply the rectified wireless power to a load; and a controller controlling the first switch so as to operate the rectifier as a full-wave rectifier or a half-wave rectifier.

Abstract: Low inductance to ground can be provided in wire-bond based device packages. An example device package may include a die on a package substrate, a mold on the package substrate and encapsulating the die, an upper ground conductor on the mold, and ground wire bonds within the mold. The die may include a plurality of terminals on an upper surface of the die. The plurality of ground wire bonds may electrically couple the die and the upper ground conductor. For each ground wire bond, a first end of that ground wire bond may be configured to electrically couple to a corresponding terminal on the upper surface of the die and a second end of that ground wire bond may be configured to electrically couple to the upper ground conductor at the upper surface of the mold.

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract: A magnetic resonance wireless power transmission device capable of adjusting resonance frequency is disclosed. A wireless power transmission device according to an embodiment of the present invention comprises: a power amplifier for amplifying a wireless power signal using a driving frequency signal; a resonator for configuring a resonance tank and wirelessly transmitting, through magnetic resonance, the wireless power signal output from the power amplifier using a resonance frequency of the resonance tank; and a resonance control unit for controlling a duty ratio using a frequency applied to the resonator or a frequency signal generated by the resonator and adjusting the resonance frequency of the resonator.

Abstract: Some features pertain to a device package that includes a die and a package substrate. The die includes a first switch. The package substrate is coupled to the die. The package substrate includes at least one dielectric layer, a primary inductor, and a first secondary inductor coupled to the first switch of the die. The first secondary inductor and the first switch are coupled to a plurality of interconnects configured to provide an electrical path for a reference ground signal. The primary inductor is configurable to have different inductances by opening and closing the first switch coupled to the first secondary inductor. In some implementations, the primary inductor is configurable in real time while the die is operational. In some implementations, the die further includes a second switch, and the package substrate further includes a second secondary inductor coupled to the second switch of the die.

Abstract: Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.

Abstract: A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

Abstract: There are provided a page buffer and a memory device having the same. A page buffer includes a reference current generation unit for precharging a bit line by generating a reference current, a current sensing unit for changing or maintaining a voltage of a select node, based on a change in current of the bit line, a first data sensing unit for storing first data, based on a change in the voltage of the select node, and a second data sensing unit for, when the first data is stored in the first data sensing unit, consecutively storing second data, based on the change in the voltage of the select node.

Abstract: The present invention relates to an electric power steering apparatus including a power transmission belt. The power transmission belt includes: an engagement part provided inside the power transmission belt where the power transmission belt is engaged with a motor pulley and a nut pulley; and a vibration reduction part provided outside the power transmission belt opposite to the engagement part. The engagement part is made of an elastic material, and the vibration reduction part is made of an elastic material that is less rigid than the engagement part. With this configuration, even if vibration and noise are generated from a motor, between the motor and a pulley, and between a belt and the pulley in the process of transmitting a torque of the motor, the vibration and the noise are reduced and prevented from being transferred to a peripheral component.

Abstract: There are provided a page buffer and a memory device having the same. A page buffer includes a reference current generation unit for precharging a bit line by generating a reference current, a current sensing unit for changing or maintaining a voltage of a select node, based on a change in current of the bit line, a first data sensing unit for storing first data, based on a change in the voltage of the select node, and a second data sensing unit for, when the first data is stored in the first data sensing unit, consecutively storing second data, based on the change in the voltage of the select node.

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Abstract: A pipe coupler may include a first coupling member and a second coupling member. The first coupling member may be configured to hold a portion of a first pipe. The second coupling member may be configured to hold a portion of a second pipe coupled to the first pipe. The first coupling member and the second coupling member may be coupled to each other to connect the first pipe to the second pipe in a direction substantially perpendicular to a coaxis of the coupled first and second pipes. Thus, a leakage of the fluid through a combining portion between the first and second coupling members may be suppressed.

Abstract: Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) having an active face, an integrated passive device (IPD) having a face, and a redistribution layer (RDL) disposed between the IPD and the IC. The IC is embedded in a substrate. The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield.

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.