Patents by Inventor Jong-hoon Lee

Jong-hoon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9576718
    Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Uei-Ming Jow, Young Kyu Song, Jong-Hoon Lee, Jung Ho Yoon, Sangjo Choi, Xiaonan Zhang
  • Publication number: 20170033059
    Abstract: A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.
    Type: Application
    Filed: July 27, 2015
    Publication date: February 2, 2017
    Inventors: Young Kyu SONG, Uei-Ming JOW, Jong-Hoon LEE
  • Publication number: 20170034195
    Abstract: An apparatus and method for detecting abnormal connection behavior are disclosed. The apparatus for detecting abnormal connection behavior includes a data extraction unit, a data storage unit, and a detection unit. The data extraction unit collects network data transmitted and received over a network including a plurality of hosts, and extracts data required for the detection of abnormal connection behavior from the network data. The data storage unit stores the extracted data required for the detection of abnormal connection behavior. The detection unit detects abnormal connection behavior based on characteristic factors corresponding to the stored data required for the detection of abnormal connection behavior and characteristic factors corresponding to malicious behavior.
    Type: Application
    Filed: January 22, 2016
    Publication date: February 2, 2017
    Inventors: Jong-Hoon LEE, Ik-Kyun KIM
  • Publication number: 20170020338
    Abstract: An agitating cooking assembly having an improved structure configured to cook food while simultaneously agitating the food, and a cooking apparatus including the same are disclosed. The cooking device includes a cooking chamber configured to provide a space in which food is cooked; a tray located at a bottom surface of the cooking chamber, and connected to a drive member generating rotational force; and an agitating cooking assembly supported by the tray and rotatable with the tray. The agitating cooking assembly includes: a cooking container configured to store food therein; an agitating member configured to agitate the food while simultaneously relatively rotating in the cooking container with respect to the cooking container; and a stopper located at a rotation path of the agitating member in a manner that the agitating member relatively rotates with respect to the cooking container.
    Type: Application
    Filed: March 23, 2015
    Publication date: January 26, 2017
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu Sik LIM, Jong Hoon LEE, Sun Hee KOO, Jeong Hee LEE, Hong Man CHANG
  • Publication number: 20160372253
    Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Uei-Ming Jow, Young Kyu Song, Jong-Hoon Lee, Jung Ho Yoon, Sangjo Choi, Xiaonan Zhang
  • Publication number: 20160365931
    Abstract: In an RN configuration for providing a new service in a PON, it is possible to configure the RN remotely by instantaneous powering from a remote site only when necessary, while the RN being operated as a PON at ordinary times. More specifically, an RN configuration for providing a new service in a PON according to the present invention includes a power generation block capable of providing energy necessary for activating the RN by instantaneously supplied power from the remote site. Further, an RN according to the present invention further includes either one or both of a control agent block capable of controlling and managing optical paths of the RN by using power generated from the power generation block; and a reconfigurable switching block capable of configuring and switching the optical path of the RN through the power being provided from the power generation block and a control by the control agent block.
    Type: Application
    Filed: December 19, 2013
    Publication date: December 15, 2016
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chang-Hee LEE, Jong-Hoon LEE, Ki-Man CHOI, Sil-Gu MUN, Jung-Hyung MOON, Hoon-Keun LEE
  • Patent number: 9443810
    Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: September 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: John Jong-Hoon Lee, Young Kyu Song, Uei-Ming Jow, Sangjo Choi, Xiaonan Zhang
  • Publication number: 20160240606
    Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 18, 2016
    Inventors: Uei-Ming JOW, Young Kyu SONG, Jong-Hoon LEE, Xiaonan ZHANG
  • Publication number: 20160240463
    Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 18, 2016
    Inventors: Uei-Ming Jow, Young Kyu Song, Jong-Hoon Lee, Xiaonan Zhang, Mario Francisco Velez
  • Publication number: 20160181541
    Abstract: Disclosed are a p-doped conjugated small molecular electrolyte containing a compound represented by Formula 1 and an organic electronic device using the same as a hole transport material. [Ar2—Ar1—Ar2]+??<Formula 1> wherein, in Formula 1, Ar1 is any one selected from the following Compound Group 1, Ar2 is any one selected from the following Compound Group 2a or the following Compound Group 2b, and superscript “+” in the square bracket indicates an oxidized portion of a main chain of the small molecule.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 23, 2016
    Inventors: Kwanghee Lee, Seoung-Ho Lee, Jong-Hoon Lee, Song-Yi Jeong
  • Patent number: 9374381
    Abstract: According to a method and system for real-time malware detection based on web browser plugin, the method and system may connect a web server of a web site through a web browser module, execute a security module through a browser plugin of the web site, update a database for a browser cache of the web site from the web server by the security module, cache a web content of the web site from the web server, match cache data of the web content with the database, and warn about the web content if data matched with the cache data of the web content does not exist in the database.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: June 21, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jung Tae Kim, Min Ho Han, Jong Hoon Lee, Ik Kyun Kim, Hyun Sook Cho
  • Patent number: 9373583
    Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: June 21, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jong-Hoon Lee, Young Kyu Song, Jung Ho Yoon, Uei Ming Jow, Xiaonan Zhang, Ryan David Lane
  • Publication number: 20160172274
    Abstract: A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die thermally coupled to a second portion of the support plate to dissipate heat, a first redistribution layer positioned in close proximity to a second redistribution layer to capacitively couple the first redistribution layer to the second redistribution layer, a first via extending between the first portion and the first redistribution layer, and a second via in close proximity to the first via to capacitively couple the second via to the first via.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Inventors: Jung Ho YOON, Young Kyu SONG, Uei-Ming JOW, Jong-Hoon LEE, Xiaonan ZHANG
  • Patent number: 9368566
    Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: June 14, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jong-Hoon Lee, Young Kyu Song, Daeik Daniel Kim, Jung Ho Yoon, Uei-Ming Jow, Mario Francisco Velez, Jonghae Kim, Xiaonan Zhang, Ryan David Lane
  • Patent number: D755835
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Jeong, Gu-Hyun Yang, Jung-Ah Seung, Bo-Ran Lee, Jong-Hoon Lee
  • Patent number: D755836
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Youn Jeong, Gu-Hyun Yang, Jung-Ah Seung, Bo-Ran Lee, Jong-Hoon Lee
  • Patent number: D755837
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bo-Ran Lee, Jae-Youn Jeong, Gu-Hyun Yang, Jung-Ah Seung, Jong-Hoon Lee
  • Patent number: D756402
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Youn Jeong, Jong-Hoon Lee, Gu-Hyun Yang
  • Patent number: D757741
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 31, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Hoon Lee, Bo-Ran Lee, Sang-Hee Bae, Gu-Hyun Yang, Jae-Youn Jeong
  • Patent number: D778919
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Hoon Lee, Bo-Ran Lee, Sang-Hee Bae, Gu-Hyun Yang, Jae-Youn Jeong