Patents by Inventor Jong-I Mou

Jong-I Mou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8889434
    Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Di Tsen, Shin-Rung Lu, Jong-I Mou
  • Publication number: 20140328534
    Abstract: Among other things, systems and techniques are provided for detecting defects on a wafer based upon non-correctable error data yielded from a scan of the wafer to determine a topology of the wafer. The non-correctable error data is reconstructed to generate a non-correctable error image map, which is transformed to generate a projection. In some embodiments, the non-correctable error image map is transformed via a feature extraction transform such as a Hough transform or a Radon transform. In some embodiments, the projection is compared to a set of rules to identify a signature in the non-correctable error image map indicative of a defect.
    Type: Application
    Filed: July 25, 2013
    Publication date: November 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: CHUN-HSIEN LIN, LIU BO-TSUN, CHIN-TI KO, WU CHENG-HUNG, KUO-HUNG CHAO, PENG JUI-CHUN, FEI-GWO TSAI, HENG-HSIN LIU, JONG-I MOU
  • Publication number: 20140303765
    Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 9, 2014
    Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
  • Patent number: 8793638
    Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keuing Hui, Yen-Wei Cheng, Yen-Di Tsen, Jong-I Mou, Chin-Hsiang Lin
  • Publication number: 20140207271
    Abstract: The present disclosure provides various methods for tuning process parameters of a process tool, including systems for implementing such tuning. An exemplary method for tuning process parameters of a process tool such that the wafers processed by the process tool exhibit desired process monitor items includes defining behavior constraint criteria and sensitivity adjustment criteria; generating a set of possible tool tuning process parameter combinations using process monitor item data associated with wafers processed by the process tool, sensitivity data associated with a sensitivity of the process monitor items to each process parameter, the behavior constraint criteria, and the sensitivity adjustment criteria; generating a set of optimal tool tuning process parameter combinations from the set of possible tool tuning process parameter combinations; and configuring the process tool according to one of the optimal tool tuning process parameter combinations.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 8781614
    Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
  • Publication number: 20140170782
    Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Di TSEN, Shin-Rung LU, Jong-I MOU
  • Publication number: 20140106474
    Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Long CHEN, Hui-Yun CHAO, Yen-Di TSEN, Jong-I MOU
  • Publication number: 20140100684
    Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chun-Hsien Lin, Jui-Long Chen, Hui-Yun Chao, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 8685759
    Abstract: The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jo Fei Wang, Sunny Wu, Jong-I Mou
  • Publication number: 20140074258
    Abstract: A method of automatically determining process parameters for processing equipment includes processing at least one first substrate in the processing equipment at a first time; and processing at least one second substrate in the processing equipment at a second time. The method includes collecting data on process monitors for the at least one first substrate; and the at least one second substrate. The method includes receiving the data by a multiple-input-multiple-output (MIMO) optimization system. The method includes revising a sensitivity matrix, by a MIMO optimizer, using the data and an adaptive-learning algorithm, wherein the adaptive-learning algorithm revises the sensitivity matrix based on a learning parameter which is related to a rate of change of the processing equipment over time. The method includes determining a set of process parameters for the processing equipment by the MIMO optimizer, wherein the MIMO optimizer uses the revised sensitivity matrix to determine the process parameters.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng TSAI, Chia-Tong HO, Sunny WU, Jo Fei WANG, Jong-I MOU
  • Publication number: 20140067324
    Abstract: The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Tong Ho, Po-Feng Tsai, Jung-Chang Chen, Tze-Liang Lee, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Publication number: 20140033159
    Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Keuing Hui, Yen-Wei Cheng, Yen-Di Tsen, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 8627251
    Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Long Chen, Hui-Yun Chao, Yen-Di Tsen, Jong-I Mou
  • Publication number: 20130335109
    Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Long Chen, Chien-Chih Liao, Tseng Chin Lo, Hui-Yun Chao, Ta-Yung Lee, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 8606387
    Abstract: A MIMO optimizer is used to identify tunable process parameters for processing equipment.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou
  • Publication number: 20130306621
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tien Chang, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Publication number: 20130288403
    Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Long CHEN, Hui-Yun CHAO, Yen-Di TSEN, Jong-I MOU
  • Patent number: 8549012
    Abstract: In accordance with an embodiment, a method for exception handling comprises accessing an exception type for an exception, filtering historical data based on at least one defined criterion to provide a data train comprising data sets, assigning a weight to each data set, and providing a current control parameter. The data sets each comprise a historical condition and a historical control parameter, and the weight assigned to each data set is based on each historical condition. The current control parameter is provided using the weight and the historical control parameter for each data set.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Feng Tsai, Jin-Ning Sung, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou
  • Publication number: 20130150997
    Abstract: A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin