Patents by Inventor Jong-I Mou

Jong-I Mou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100255613
    Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method for fabricating ICs from a semiconductor wafer comprising performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; and using the first measurement to generate metrology calibration data, wherein the metrology calibration data includes an effective portion and a non-effective portion. The method further comprises removing the non-effective portion from the metrology calibration data and modeling the effective portion with a metrology calibration model; combining the metrology calibration model with a first process model to generate a multi-resolution model, wherein the first process model models an input-output relationship of the first process; and analyzing a response of the multi-resolution model and second measurement data to control performance a second process.
    Type: Application
    Filed: April 1, 2009
    Publication date: October 7, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Andy Tsen, Jin-Ning Sung, Po-Feng Tsai, Jong-I Mou
  • Publication number: 20100248398
    Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jo Fei Wang, Sunny Wu, Jong-I Mou
  • Publication number: 20100250172
    Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Andy Tsen, Sunny Wu, Wang Jo Fei, Jong-I Mou
  • Publication number: 20100249974
    Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a first plurality of semiconductor wafers; determining a sampling rate to the first plurality of semiconductor wafers based on process quality; determining sampling fields and sampling points to the first plurality of semiconductor wafers; measuring a subset of the first plurality of semiconductor wafers according to the sampling arte, the sampling fields and the sampling points; modifying a second process according to the measuring; and applying the second process to a second plurality of semiconductor waders.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wang Jo Fei, Andy Tsen, Ming-Yu Fan, Jill Wang, Jong-I Mou
  • Publication number: 20100228370
    Abstract: A method of advanced process control (APC) for semiconductor fabrication is provided. The method includes providing a present wafer to be processed by a semiconductor processing tool, providing first data of previous wafers that have been processed by the semiconductor processing tool, decoupling noise from the first data to generate second data, evaluating an APC performance based on proximity of the second data to a target data, determining a control parameter based on the APC performance, and controlling the semiconductor processing tool with the control parameter to process the present wafer.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 9, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Andy Tsen, Chih-Wei Hsu, Ming-Yeon Hung, Ming-Yu Fan, Wang Jo Fei, Jong-I Mou
  • Publication number: 20100210041
    Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 19, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
  • Publication number: 20070090722
    Abstract: A planar micro parallel-link mechanism that provides fine planar motion to a platform in two translation directions and one rotation direction using comb-drive actuators with gear chain systems coupled to rack-and-pinions and struts. The micro parallel-link mechanism has a large operating envelope and can be fabricated using surface micromachining techniques. The kinematic and dynamic analyses of the micro parallel-link mechanism are integrated with closed-loop control system to monitor and supervise the position and velocity of the micro mechanism with three degree-of freedom motions. Methods of depositing and building miniaturized tools and parts on the platform are also disclosed to provide the basic building block for a number of products applicable for nano technology, sensor, actuators, and biotechnology applications.
    Type: Application
    Filed: March 11, 2004
    Publication date: April 26, 2007
    Inventors: Jong-I Mou, Chi-Te Chin