Patents by Inventor Jong-ryeol Yoo
Jong-ryeol Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10892347Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: GrantFiled: November 21, 2018Date of Patent: January 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung Yub Jeon, Tae Yong Kwon, Oh Seong Kwon, Soo Yeon Jeong, Yong Hee Park, Jong Ryeol Yoo
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Patent number: 10644158Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including an active pattern protruding from a substrate; a plurality of gate structures each including a gate electrode and crossing the active pattern; and a source/drain region between the plurality of gate structures, wherein the source/drain region includes a high concentration doped layer in contact with a bottom surface of a recessed region in the active pattern, a first epitaxial layer in contact with an upper surface of the high concentration doped layer and a sidewall of the recessed region, and a second epitaxial layer on the first epitaxial layer, and the high concentration doped layer has a first area in contact with the bottom surface of the recessed region and a second area in contact with the sidewall of the recessed region, the first area being wider than the second area.Type: GrantFiled: October 17, 2018Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Su Jin Jung, Jeong Ho Yoo, Jong Ryeol Yoo, Young Dae Cho
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Publication number: 20190296144Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including an active pattern protruding from a substrate; a plurality of gate structures each including a gate electrode and crossing the active pattern; and a source/drain region between the plurality of gate structures, wherein the source/drain region includes a high concentration doped layer in contact with a bottom surface of a recessed region in the active pattern, a first epitaxial layer in contact with an upper surface of the high concentration doped layer and a sidewall of the recessed region, and a second epitaxial layer on the first epitaxial layer, and the high concentration doped layer has a first area in contact with the bottom surface of the recessed region and a second area in contact with the sidewall of the recessed region, the first area being wider than the second area.Type: ApplicationFiled: October 17, 2018Publication date: September 26, 2019Inventors: Su Jin JUNG, Jeong Ho YOO, Jong Ryeol YOO, Young Dae CHO
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Publication number: 20190252540Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Inventors: Sung-Min Kim, Kyung-Seok Oh, Cheol Kim, Heon-Jong Shin, Jong-Ryeol Yoo, Hyun-Jung Lee, Seong-Hoon Jeong
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Patent number: 10319858Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.Type: GrantFiled: September 11, 2018Date of Patent: June 11, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Kyung-Seok Oh, Cheol Kim, Heon-Jong Shin, Jong-Ryeol Yoo, Hyun-Jung Lee, Seong-Hoon Jeong
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Publication number: 20190109214Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: ApplicationFiled: November 21, 2018Publication date: April 11, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Yub JEON, Tae Yong KWON, Oh Seong KWON, Soo Yeon JEONG, Yong Hee PARK, Jong Ryeol YOO
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Publication number: 20190013401Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.Type: ApplicationFiled: September 11, 2018Publication date: January 10, 2019Inventors: Sung-Min KIM, Kyung-Seok OH, Cheol KIM, Heon-Jong SHIN, Jong-Ryeol YOO, Hyun-Jung LEE, Seong-Hoon JEONG
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Patent number: 10164057Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: GrantFiled: January 24, 2018Date of Patent: December 25, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung Yub Jeon, Tae Yong Kwon, Oh Seong Kwon, Soo Yeon Jeong, Yong Hee Park, Jong Ryeol Yoo
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Publication number: 20180350952Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: ApplicationFiled: January 24, 2018Publication date: December 6, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Yub JEON, Tae Yong KWON, Oh Seong KWON, Soo Yeon JEONG, Yong Hee PARK, Jong Ryeol YOO
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Patent number: 10103266Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.Type: GrantFiled: April 20, 2015Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Kyung-Seok Oh, Cheol Kim, Heon-Jong Shin, Jong-Ryeol Yoo, Hyun-Jung Lee, Seong-Hoon Jeong
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Publication number: 20160005852Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.Type: ApplicationFiled: April 20, 2015Publication date: January 7, 2016Inventors: Sung-Min Kim, Kyung-Seok Oh, Cheol Kim, Heon-Jong Shin, Jong-Ryeol Yoo, Hyun-Jung Lee, Seong-Hoon Jeong
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Patent number: 9190495Abstract: A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.Type: GrantFiled: September 21, 2009Date of Patent: November 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Do Ryu, Dong-Chan Kim, Seong-Hoon Jeong, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Jong-Ryeol Yoo, Jong-Hoon Kang
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Publication number: 20140367774Abstract: Semiconductor devices are provided including a first trench in a semiconductor substrate; a first insulating film in the first trench; a first conductive film on the first insulating film, the first conductive film having upper and lower portions and filling at least a portion of the first trench; and a first work function adjustment film having first and second portions, a first lower work function adjustment film portion and a first upper work function adjustment portion. The first lower work function adjustment film portion overlaps the lower portion of the first conductive film and the first upper work function adjustment film portion overlaps the upper portion of the first conductive film between the first insulating film and the first conductive film.Type: ApplicationFiled: June 3, 2014Publication date: December 18, 2014Inventors: Jong-Ryeol Yoo, Jun-Noh Lee, Dong-Chan Kim, Han-Jin Lim
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Patent number: 8691649Abstract: In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.Type: GrantFiled: June 2, 2011Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tai-Su Park, Jung-Sup Oh, Gun-Joong Lee, Jung-Soo An, Dong-Kyu Lee, Jung-Geun Park, Jeong-Do Ryu, Dong-Chan Kim, Seong-Hoon Jeong, Si-Young Choi, Yu-Gyun Shin, Jong-Ryeol Yoo, Jong-Hoon Kang
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Patent number: 8501611Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.Type: GrantFiled: July 17, 2012Date of Patent: August 6, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Do Ryu, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Dong-Chan Kim, Jong-Ryeol Yoo, Seong-Hoon Jeong, Jong-Hoon Kang
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Publication number: 20120282769Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Inventors: Jeong-Do Ryu, Si-Young CHOI, Yu-Gyun SHIN, Tai-Su PARK, Dong-Chan KIM, Jong-Ryeol YOO, Seong-Hoon JEONG, Jong-Hoon KANG
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Patent number: 8252681Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.Type: GrantFiled: August 6, 2009Date of Patent: August 28, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Do Ryu, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Dong-Chan Kim, Jong-Ryeol Yoo, Seong-Hoon Jeong, Jong-Hoon Kang
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Patent number: 8168521Abstract: In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.Type: GrantFiled: March 17, 2010Date of Patent: May 1, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: In-Sang Jeon, Si-Hyung Lee, Jong-Ryeol Yoo, Yu-Ghun Shin, Suk-Hun Choi
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Patent number: 8034701Abstract: Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.Type: GrantFiled: July 31, 2009Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Chang-Won Lee, Hee-Sook Park, Woong-Hee Sohn, Sun-Pil Youn, Jong-ryeol Yoo
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Publication number: 20110237037Abstract: In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.Type: ApplicationFiled: June 2, 2011Publication date: September 29, 2011Inventors: Tai-Su Park, Jung-Sup Oh, Gun-Joong Lee, Jung-Soo An, Dong-Kyu Lee, Jung-Geun Park, Jeong-Do Ryu, Dong-Chan Kim, Seong-Hoon Jeong, Si-Young Choi, Yu-Gyun Shin, Jong-Ryeol Yoo, Jong-Hoon Kang