Patents by Inventor Jong Sam Kim
Jong Sam Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961679Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.Type: GrantFiled: November 2, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Woo Kim, Eun Jung Lee, Jong Suk Jeong, Chun Hee Seo, Jong Hoon Yoo, Tae Hyung Kim, Ho Sam Choi, Sim Chung Kang
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Publication number: 20240104115Abstract: Disclosed herein are a method and apparatus for converting a credential data schema.Type: ApplicationFiled: July 11, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seok-Hyun KIM, Soo-Hyung KIM, Young-Seob CHO, Geon-Woo KIM, Young-Sam KIM, Jong-Hyouk NOH, Kwan-Tae CHO, Sang-Rae CHO, Jin-Man CHO, Seung-Hun JIN
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Publication number: 20240101272Abstract: The present disclosure relates to a system and method for detecting an aircraft energy anomaly using an artificial neural network learning model. A system for detecting an aircraft energy anomaly using an artificial neural network learning model according to the present disclosure includes an input interface device for receiving ADS-B (Automatic Dependent Surveillance-Broadcast) data, a memory storing a program which generates a specific energy feature for energy state analysis by extending the ADS-B data through a preprocessing, and a processor for executing the program, wherein the processor generates an energy distribution model by the use of the specific energy feature, and performs artificial neural network-based energy anomaly learning.Type: ApplicationFiled: July 10, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Noh-Sam PARK, Ji Yeon KIM, Jong Hyun JANG
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Publication number: 20240104990Abstract: Disclosed herein is a method for user-centered visitor access management, which may include issuing, by a management office server, a digital certificate to a householder terminal; registering, by a wall-pad, a householder in response to a request to register the householder based on the digital certificate; requesting, by the householder terminal, the management office server to register a visitor based on a visit request from a visitor terminal and delegating the digital certificate to the visitor terminal; making an entry request to a management terminal based on the digital certificate; verifying, by the wall-pad, the digital certificate based on a request for verification for entry from a wall-pad management terminal and providing a verification result to the wall-pad management terminal when the management terminal is the wall-pad management terminal; and managing and controlling, by the wall-pad, permission to use home devices based on delegated permission information of the digital certificate.Type: ApplicationFiled: March 22, 2023Publication date: March 28, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seok-Hyun KIM, Young-Seob CHO, Soo-Hyung KIM, Geon-Woo KIM, Young-Sam KIM, Jong-Hyouk NOH, Kwan-Tae CHO, Sang-Rae CHO, Jin-Man CHO, Seung-Hun JIN
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Patent number: 10672498Abstract: A repair device and a semiconductor device including the same are disclosed, which relate to a technology for a Post Package Repair (PPR) device. The repair device includes: a clock generator configured to generate a fuse clock signal based to corresponding to an available fuse; a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal; a fuse signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; and an output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses.Type: GrantFiled: February 2, 2018Date of Patent: June 2, 2020Assignee: SK hynix Inc.Inventor: Jong Sam Kim
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Patent number: 10325669Abstract: An error information storage circuit configured to write information stored in a plurality of fuse sets to a plurality of fuse latch sets of a core block and/or to write test data to the plurality of fuse latch sets. The test data is internally generated depending on a fuse clock signal, and the test data has values which cause opposite levels to be written in adjacent latches of the plurality of fuse latch sets.Type: GrantFiled: May 15, 2018Date of Patent: June 18, 2019Assignee: SK hynix Inc.Inventor: Jong Sam Kim
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Publication number: 20190130985Abstract: An error information storage circuit configured to write information stored in a plurality of fuse sets to a plurality of fuse latch sets of a core block and/or to write test data to the plurality of fuse latch sets. The test data is internally generated depending on a fuse clock signal, and the test data has values which cause opposite levels to be written in adjacent latches of the plurality of fuse latch sets.Type: ApplicationFiled: May 15, 2018Publication date: May 2, 2019Applicant: SK hynix Inc.Inventor: Jong Sam KIM
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Patent number: 10229876Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.Type: GrantFiled: March 17, 2016Date of Patent: March 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Jung Kim, Young-Bae Kim, Jong-Sam Kim, Jin-Hyeung Park, Jeong-Hoon Ahn, Hyeok-Sang Oh, Kyoung-Woo Lee, Hyo-Seon Lee, Suk-Hee Jang
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Publication number: 20190051371Abstract: A repair device and a semiconductor device including the same are disclosed, which relate to a technology for a Post Package Repair (PPR) device. The repair device includes: a clock generator configured to generate a fuse clock signal based to corresponding to an available fuse; a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal; a fuse signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; and an output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses.Type: ApplicationFiled: February 2, 2018Publication date: February 14, 2019Inventor: Jong Sam KIM
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Patent number: 10007454Abstract: A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.Type: GrantFiled: November 14, 2016Date of Patent: June 26, 2018Assignee: SK hynix Inc.Inventors: Jong Sam Kim, Jong Yeol Yang
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Patent number: 9991786Abstract: An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal by performing a boot-up operation in response to the driving signal outputted from the power driving unit.Type: GrantFiled: October 19, 2015Date of Patent: June 5, 2018Assignee: SK hynix Inc.Inventors: Jong Sam Kim, Jong Yeol Yang
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Patent number: 9978463Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.Type: GrantFiled: January 23, 2017Date of Patent: May 22, 2018Assignee: SK hynix Inc.Inventors: Jong Sam Kim, Jin Hee Cho
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Patent number: 9915964Abstract: A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.Type: GrantFiled: January 7, 2015Date of Patent: March 13, 2018Assignee: SK hynix Inc.Inventor: Jong Sam Kim
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Publication number: 20180059967Abstract: A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.Type: ApplicationFiled: November 14, 2016Publication date: March 1, 2018Inventors: Jong Sam KIM, Jong Yeol YANG
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Patent number: 9886339Abstract: A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. The redundancy memory cells may be coupled to a plurality of word lines and bit lines, and may replace one or more normal memory cells that are defective. The fuse array may include a redundancy address storage region configured to store addresses of the redundancy memory cells, an error correction information storage region configured to store error correction information for correcting errors of addresses of the redundancy memory cells, stored in the redundancy address storage region, and a weak address storage region configured to store an address of a weak cell among the normal memory cells. The controller may perform a repair operation based on a redundancy address and perform a refresh operation on a weak cell corresponding to the address of the weak cell.Type: GrantFiled: August 23, 2016Date of Patent: February 6, 2018Assignee: SK hynix Inc.Inventor: Jong Sam Kim
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Patent number: 9859024Abstract: A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.Type: GrantFiled: May 23, 2016Date of Patent: January 2, 2018Assignee: SK Hynix Inc.Inventors: Jong-Sam Kim, Jae-Il Kim
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Patent number: 9847142Abstract: A semiconductor apparatus includes a fuse array configured to store word line failure information, a redundancy latch section, and a redundancy control block configured to store, in the redundancy latch section, word line order information generated according to the word line failure information.Type: GrantFiled: October 22, 2015Date of Patent: December 19, 2017Assignee: SK hynix Inc.Inventors: Jong Sam Kim, Jin Hee Cho
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Patent number: 9818491Abstract: A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.Type: GrantFiled: March 2, 2016Date of Patent: November 14, 2017Assignee: SK Hynix Inc.Inventors: Jong-Sam Kim, Jae-Il Kim
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Publication number: 20170269989Abstract: A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. The redundancy memory cells may be coupled to a plurality of word lines and bit lines, and may replace one or more normal memory cells that are defective. The fuse array may include a redundancy address storage region configured to store addresses of the redundancy memory cells, an error correction information storage region configured to store error correction information for correcting errors of addresses of the redundancy memory cells, stored in the redundancy address storage region, and a weak address storage region configured to store an address of a weak cell among the normal memory cells. The controller may perform a repair operation based on a redundancy address and perform a refresh operation on a weak cell corresponding to the address of the weak cell.Type: ApplicationFiled: August 23, 2016Publication date: September 21, 2017Inventor: Jong Sam KIM
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Patent number: 9736023Abstract: Provided are an apparatus and a method for changing a status of cluster nodes, which determine whether to change statuses of respective cluster nodes themselves to an active status or a standby status without intervention by a manager through self-diagnosis and change the status of the nodes.Type: GrantFiled: October 30, 2014Date of Patent: August 15, 2017Assignee: SAMSUNG SDS CO., LTD.Inventors: Jong Sam Kim, Ho Young Son, Hyun Soo Kim, Tack Su An