Abstract: A memory device includes a plurality of stacked slice chips. The plurality of slice chips are electrically connected to each other through a plurality of through-vias, and when one of the plurality of slice chips is chip-killed, the operation of the plurality of slice chips is determined by correcting a slice ID in each of the plurality of slice chips. In addition, among the slice chips that are not chip-killed among the plurality of slice chips, a slice chip at a lowest layer and a slice chip at a highest layer are determined to operate.

Abstract: A repair device and a semiconductor device including the same are disclosed, which relate to a technology for a Post Package Repair (PPR) device. The repair device includes: a clock generator configured to generate a fuse clock signal based to corresponding to an available fuse; a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal; a fuse signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; and an output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses.

Abstract: An error information storage circuit configured to write information stored in a plurality of fuse sets to a plurality of fuse latch sets of a core block and/or to write test data to the plurality of fuse latch sets. The test data is internally generated depending on a fuse clock signal, and the test data has values which cause opposite levels to be written in adjacent latches of the plurality of fuse latch sets.

Abstract: An error information storage circuit configured to write information stored in a plurality of fuse sets to a plurality of fuse latch sets of a core block and/or to write test data to the plurality of fuse latch sets. The test data is internally generated depending on a fuse clock signal, and the test data has values which cause opposite levels to be written in adjacent latches of the plurality of fuse latch sets.

Abstract: A repair device and a semiconductor device including the same are disclosed, which relate to a technology for a Post Package Repair (PPR) device. The repair device includes: a clock generator configured to generate a fuse clock signal based to corresponding to an available fuse; a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal; a fuse signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; and an output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses.

Abstract: A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.

Abstract: An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal by performing a boot-up operation in response to the driving signal outputted from the power driving unit.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.

Abstract: A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.

Abstract: A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. The redundancy memory cells may be coupled to a plurality of word lines and bit lines, and may replace one or more normal memory cells that are defective. The fuse array may include a redundancy address storage region configured to store addresses of the redundancy memory cells, an error correction information storage region configured to store error correction information for correcting errors of addresses of the redundancy memory cells, stored in the redundancy address storage region, and a weak address storage region configured to store an address of a weak cell among the normal memory cells. The controller may perform a repair operation based on a redundancy address and perform a refresh operation on a weak cell corresponding to the address of the weak cell.

Abstract: A semiconductor apparatus includes a fuse array configured to store word line failure information, a redundancy latch section, and a redundancy control block configured to store, in the redundancy latch section, word line order information generated according to the word line failure information.

Abstract: A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. The redundancy memory cells may be coupled to a plurality of word lines and bit lines, and may replace one or more normal memory cells that are defective. The fuse array may include a redundancy address storage region configured to store addresses of the redundancy memory cells, an error correction information storage region configured to store error correction information for correcting errors of addresses of the redundancy memory cells, stored in the redundancy address storage region, and a weak address storage region configured to store an address of a weak cell among the normal memory cells. The controller may perform a repair operation based on a redundancy address and perform a refresh operation on a weak cell corresponding to the address of the weak cell.

Abstract: Provided are an apparatus and a method for changing a status of cluster nodes, which determine whether to change statuses of respective cluster nodes themselves to an active status or a standby status without intervention by a manager through self-diagnosis and change the status of the nodes.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: A semiconductor apparatus includes a fuse array configured to store word line failure information, a redundancy latch section, and a redundancy control block configured to store, in the redundancy latch section, word line order information generated according to the word line failure information.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal to by performing a boot-up operation in response to the driving signal outputted from the power driving unit.

Abstract: A voltage generation circuit of a semiconductor apparatus includes a first detection block configured to detect an output voltage and output a first detection signal; a second detection block configured to detect the output voltage and output a second detection signal; a signal generation block configured to generate a control signal in response to the first detection signal and the second detection signal; and a voltage generation block configured to generate the output voltage in response to the control signal, wherein responding speeds of the first detection block and the second detection block with respect to a variation in the output voltage are different.