Abstract: A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.

Abstract: A semiconductor device may include normal memory cells, redundancy memory cells, a fuse array, and a controller. The normal memory cells may be coupled to a plurality of word lines and bit lines. The redundancy memory cells may be coupled to a plurality of word lines and bit lines, and may replace one or more normal memory cells that are defective. The fuse array may include a redundancy address storage region configured to store addresses of the redundancy memory cells, an error correction information storage region configured to store error correction information for correcting errors of addresses of the redundancy memory cells, stored in the redundancy address storage region, and a weak address storage region configured to store an address of a weak cell among the normal memory cells. The controller may perform a repair operation based on a redundancy address and perform a refresh operation on a weak cell corresponding to the address of the weak cell.

Abstract: Provided are an apparatus and a method for changing a status of cluster nodes, which determine whether to change statuses of respective cluster nodes themselves to an active status or a standby status without intervention by a manager through self-diagnosis and change the status of the nodes.

Abstract: A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.

Abstract: A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: A semiconductor apparatus includes a fuse array configured to store word line failure information, a redundancy latch section, and a redundancy control block configured to store, in the redundancy latch section, word line order information generated according to the word line failure information.

Abstract: An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal to by performing a boot-up operation in response to the driving signal outputted from the power driving unit.

Abstract: A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

Abstract: A voltage generation circuit of a semiconductor apparatus includes a first detection block configured to detect an output voltage and output a first detection signal; a second detection block configured to detect the output voltage and output a second detection signal; a signal generation block configured to generate a control signal in response to the first detection signal and the second detection signal; and a voltage generation block configured to generate the output voltage in response to the control signal, wherein responding speeds of the first detection block and the second detection block with respect to a variation in the output voltage are different.

Abstract: A semiconductor memory apparatus may include a chip area configured to include one or more semiconductor memory chips. The semiconductor memory apparatus may include a repair system configured to perform a test for the chip area while the chip area is in a test mode, to determine whether the chip area has been repaired, and to generate the determination of whether the chip area has been repaired as quality information in response to a failure detection signal enabled while the chip area is in the test mode.

Abstract: A semiconductor apparatus includes a reference voltage generation unit configured to generate a reference voltage. The semiconductor apparatus also includes an internal voltage generation unit configured to generate an internal voltage which corresponds to a voltage level of the reference voltage. In addition, the semiconductor apparatus includes a noise generation unit configured to generate noise in the reference voltage according to noise of the internal voltage.

Abstract: A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

Abstract: A semiconductor apparatus may include a global line configured to enable electrical coupling between a memory block and an input/output terminal, a fuse array configured to store and to transmit repair information through the global line, and a control unit configured to selectively enable or disable signal paths among the input/output terminal, the global line, and the fuse array according to an operation mode of the semiconductor apparatus.

Abstract: A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.

Abstract: A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

Abstract: A semiconductor apparatus may include a global line configured to enable electrical coupling between a memory block and an input/output terminal, a fuse array configured to store and to transmit repair information through the global line, and a control unit configured to selectively enable or disable signal paths among the input/output terminal, the global line, and the fuse array according to an operation mode of the semiconductor apparatus.