Patents by Inventor Jong-su Kim

Jong-su Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200344853
    Abstract: An inorganic electroluminescence device having heat resistance, moisture resistance and physical durability improved by applying a transparent electrode layer including a metal mesh substrate or a metal patterned substrate, and a method for manufacturing the same.
    Type: Application
    Filed: November 26, 2019
    Publication date: October 29, 2020
    Inventors: Hong Chan Jeon, Mi Jung Yun, Oh Deok Kwon, Hyung Joon Youn, Afandi Mohammad Malik, Jong Su Kim, Tae Wook Kang, Jong Ho Ryu
  • Publication number: 20200263003
    Abstract: The present disclosure relates to a polyarylene sulfide resin composition for an automobile headlamp component, a method for producing the same, and an automobile headlamp component manufactured using the same. The polyarylene sulfide resin composition includes: about 45 wt % to about 75 wt % of a polyarylene sulfide resin containing about 300 ppm or less of chlorine; about 24.5 wt % to about 55 wt % of an inorganic filler; about 0.1 wt % to about 1 wt % of a nucleating agent; about 0.05 wt % to about 1 wt % of metal powder; and about 0.1 wt % to about 2.5 wt % of a composite metal hydroxide.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 20, 2020
    Inventors: Jong Su Kim, Seung Yeon Lee, Jung Hwan Lee, Ya Won Kim, Hyeong Geun Oh, Jong Wook Shin, Se Ran Choi
  • Patent number: 10735427
    Abstract: An electronic device and a program management method therefor are provided. The electronic device includes a communication interface, a memory, at least one processor, and a secure circuitry. The secure circuitry is configured to provide a first public key stored in the secure circuitry to the at least one processor. The at least one processor is configured to transmit the first public key to an external device and receive an encrypted secure program encrypted based on the first public key and a second public key generated by the external device, from the external device. The at least one processor is further configured to transmit the second public key and the encrypted secure program to the secure circuitry. The secure circuitry is configured to decrypt the encrypted secure program based on the second public key and a first private key which is symmetrical to the first public key.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Young Kwon, Yang Keun Kim, Jong Su Kim, Taeck Ki Lee, Dae Haeng Cho, Chol Seo Park, Da Som Lee
  • Patent number: 10724967
    Abstract: An inspection apparatus for a semiconductor process and a semiconductor process device, the inspection apparatus including a transferer configured to transfer a process object between a plurality of chambers; at least one line camera installed above the transferer, the at least one line camera being configured to generate an original image by capturing an image of the process object transferred by the transferer; and a controller configured to receive the original image and to perform an inspection of the process object by correcting distortion of the original image due to a change in transfer speed of the transferer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Ho Jung, Young Su Ryu, Sung Chai Kim, Jong Su Kim, Won Guk Seo, Chang Hoon Choi, Jeong Su Ha
  • Patent number: 10643888
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Publication number: 20200108692
    Abstract: The present invention relates to a perforated member and an air conditioner for a vehicle having the same, which can solve the heat pick-up problem of a two-layered structure and enhance manufacturing performance and assemblability even though a space between a heater core and an electric heater is divided.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 9, 2020
    Inventors: Dong Won LEE, Jong Su KIM, Jae Woo KO, Young Keun KIM, Chang Soo BAE, Jong Min LEE, Gyu Ik HAN
  • Publication number: 20200065081
    Abstract: An electronic device includes a secure element in which at least one application package is installed and a processor for communicating with the secure element. The secure element further stores a list with which a part or all of identification information of the at least one application package is registered. The processor controls the secure element such that an application package indicated by the identification information registered with the list is uninstalled, in response to a specified event. Various other embodiments recognized from the specification are also possible.
    Type: Application
    Filed: November 20, 2017
    Publication date: February 27, 2020
    Inventors: Taeck Ki LEE, Dae Haeng CHO, Eun Young KWON, Jong Su KIM, Da Som LEE
  • Patent number: 10533143
    Abstract: The present invention relates to a combustor-independent fluidized bed indirect gasification system for technology for obtaining high quality synthetic gas through effective indirect gasification of low quality fuels, such as biomass/waste/coal, having various properties, and provides a combustor-independent fluidized bed indirect gasification system comprising: a pre-processor having a sorter 500; a gasifier 300 to which a first fuel sorted in the pre-processor is supplied; a combustor 100 to which a second fuel sorted in the pre-processor is supplied; and a riser 200 connecting the gasifier 300 and the combustor 100 and having functions of increasing the temperature of a bed material and transferring the bed material therein.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: January 14, 2020
    Assignee: KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY
    Inventors: Uen Do Lee, Byung Ryeul Bang, Chang Won Yang, Jong Su Kim, Tae U Yu
  • Publication number: 20190355848
    Abstract: A semiconductor device includes a substrate, and a first source/drain region formed on the substrate. The semiconductor device further includes a channel formed on the first source/drain region, and a second source/drain region formed on the channel. The semiconductor device also includes a gate electrode formed on an external surface of the channel, and a metal pad formed on the substrate. The height of an upper surface of the metal pad is the same as the length of an upper surface of the gate electrode.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventor: Jong Su Kim
  • Publication number: 20190323973
    Abstract: An inspection apparatus for a semiconductor process and a semiconductor process device, the inspection apparatus including a transferer configured to transfer a process object between a plurality of chambers; at least one line camera installed above the transferer, the at least one line camera being configured to generate an original image by capturing an image of the process object transferred by the transferer; and a controller configured to receive the original image and to perform an inspection of the process object by correcting distortion of the original image due to a change in transfer speed of the transferer.
    Type: Application
    Filed: January 8, 2019
    Publication date: October 24, 2019
    Inventors: Myung Ho JUNG, Young Su RYU, Sung Chai KIM, Jong Su KIM, Won Guk SEO, Chang Hoon CHOI, Jeong Su HA
  • Patent number: 10446444
    Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 10403751
    Abstract: A semiconductor device includes a substrate, and a first source/drain region formed on the substrate. The semiconductor device further includes a channel formed on the first source/drain region, and a second source/drain region formed on the channel. The semiconductor device also includes a gate electrode formed on an external surface of the channel, and a metal pad formed on the substrate. The height of an upper surface of the metal pad is the same as the length of an upper surface of the gate electrode.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Su Kim
  • Patent number: 10319419
    Abstract: A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventors: Jong-Su Kim, Yeon-Gul Jung
  • Publication number: 20190168571
    Abstract: The present invention relates to an air conditioner for a vehicle, which includes an air-conditioning case (200), and at least one door (100) mounted to be opened and closed at a predetermined position, wherein the door (100) is formed integrally with an arm pivot (140), and the arm pivot (140) includes a pin part, and ribs formed integrally with both sides of the pin part to reinforce rigidity of the pin part and offset noise. The air conditioner further includes distortion preventing parts formed on a rotary shaft to be dented and to be crossed to each other, thereby reducing a transformation rate of the door and securing accuracy of the pin part.
    Type: Application
    Filed: December 7, 2017
    Publication date: June 6, 2019
    Inventors: Jong Su KIM, Seong Seok HAN, Jeong Jae LEE, Hyung Joo KIM, Hun Sang LEE, Heon HUR, Beom Ki KIM
  • Publication number: 20190113838
    Abstract: A method of designing a layout of a photomask and a method of manufacturing a photomask, the method of designing a layout of a photomask including obtaining a design layout of a mask pattern; performing an optical proximity correction on the design layout to obtain design data; obtaining data of a position error of a pattern occurring during an exposure of the photomask according to the design data; correcting position data of the pattern based on the position error data to correct the design data; and providing the corrected position data to an exposure device to expose an exposure beam according to the corrected design data.
    Type: Application
    Filed: March 28, 2018
    Publication date: April 18, 2019
    Inventors: Yong-Seok Jung, Sung-Hoon Park, Jong-Su Kim, Suk-Jong Bae
  • Publication number: 20190088546
    Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive to pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.
    Type: Application
    Filed: November 21, 2018
    Publication date: March 21, 2019
    Applicant: SK hynix Inc.
    Inventor: Jong Su KIM
  • Publication number: 20190031823
    Abstract: The present invention relates to a polyester resin composition and a molded article produced therefrom. The polyester resin composition includes: about 80 wt % to about 98 wt % of a polybutylene terephthalate resin; about 0.1 wt % to about 5 wt % of a carbodiimide-based compound; about 0.1 wt % to about 5 wt % of a nucleating agent; and about 0.5 wt % to about 15 wt % of an inorganic filler having a non-spherical or non-circular cross-section.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 31, 2019
    Inventors: Seung Yeon LEE, Jong Su KIM, Jung Hwan LEE, Jung Won KIM, Yi Seul JEON, Min Cheol SHIN, Soo Min LEE
  • Patent number: 10170363
    Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 1, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 10153272
    Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: December 11, 2018
    Assignee: SK hynix Inc.
    Inventor: Jong Su Kim
  • Publication number: 20180345421
    Abstract: A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core includes: (a) pure silver consisting of silver and further components; or (b) doped silver consisting of silver, at least one doping element, and further components; or (c) a silver alloy consisting of silver, palladium and further components; or (d) a silver alloy consisting of silver, palladium, gold, and further components; or (e) a doped silver alloy consisting of silver, palladium, gold, at least one doping element, and further components, wherein the individual amount of any further component is less than 30 wt.-ppm and the individual amount of any doping element is at least 30 wt.-ppm, and the coating layer is a single-layer of gold or palladium or a double-layer comprised of an inner layer of nickel or palladium and an adjacent outer layer of gold.
    Type: Application
    Filed: September 16, 2016
    Publication date: December 6, 2018
    Applicants: Heraeus Materials Singapore Pte., Ltd., Heraeus Oriental HiTec Co., Ltd.
    Inventors: Il Tae Kang, Yong-Deok Tark, Mong Hyun Cho, Jong Su Kim, Hyun Seok Jung, Tae Yeop Kim, Xi Zhang, Murali Sarangapani