Abstract: An electronic apparatus and a method for performing a settlement transaction in an electronic apparatus, according to various embodiments of the present invention, can transmit, to a settlement apparatus, settlement data, which is generated by using authentication information, in response to a settlement request inputted through the electronic apparatus; check whether a settlement response message including result information of a settlement performance using the settlement data is received; and manage stored authentication information according to whether the settlement response message is received within a predetermined time period. Also, other various embodiments are possible.

Abstract: An electronic device is provided. The electronic device includes a processor, a memory configured to connect to the processor, and an embedded secure element (eSE) configured to connect to the processor over a physical channel to receive secure data sent by the processor over the physical channel, and store the secure data.

Abstract: A semiconductor integrated circuit device may include a cell capacitor connected with any one of a first electrode and a second electrode of an access device. The cell capacitor may include a first cell cap array and a second cell cap array separated from the first cell cap array. A voltage terminal for driving the cell capacitor may be connected to a connection node between the first cell cap array and the second cell cap array.

Abstract: A semiconductor device includes a substrate, and a first source/drain region formed on the substrate. The semiconductor device further includes a channel formed on the first source/drain region, and a second source/drain region formed on the channel. The semiconductor device also includes a gate electrode formed on an external surface of the channel, and a metal pad formed on the substrate. The height of an upper surface of the metal pad is the same as the length of an upper surface of the gate electrode.

Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

Abstract: A method of manufacturing a reticle, the method including preparing a substrate, determining position data of a pattern to be formed on the substrate, and setting a primary exposure condition to form the pattern; performing a primary exposure simulation regarding the substrate based on the position data of the pattern and the primary exposure condition; calculating a primary deformation rate of the substrate, which is generated in the primary exposure simulation; correcting the position data of the pattern based on the primary deformation rate of the substrate to provide a corrected position data of the pattern; and exposing the substrate under the primary exposure condition based on the corrected position data of the pattern.

Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.

Abstract: A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.

Abstract: An electronic device and a program management method therefor are provided. The electronic device includes a communication interface, a memory, at least one processor, and a secure circuitry. The secure circuitry is configured to provide a first public key stored in the secure circuitry to the at least one processor. The at least one processor is configured to transmit the first public key to an external device and receive an encrypted secure program encrypted based on the first public key and a second public key generated by the external device, from the external device. The at least one processor is further configured to transmit the second public key and the encrypted secure program to the secure circuitry. The secure circuitry is configured to decrypt the encrypted secure program based on the second public key and a first private key which is symmetrical to the first public key.

Abstract: The present invention relates to a simultaneous analysis method for a target using a plurality of metal nano-tags and, more particularly, to a simultaneous analysis method for a target using a plurality of metal nano-tags, wherein the method fuses a nano-particle technology on the basis of an antigen-antibody reaction, which is a conventional biological immune response, and simultaneously diagnoses a plurality of target materials by using a plurality of antigen-antibody reactions and a plurality of metal nano-tags, thereby enhancing diagnostic effect.

Abstract: A sense amplifier may be provided. The sense amplifier may include a first switch coupled between any one of a first signal line pair and a first power supply terminal. The sense amplifier may include a second switch coupled between the other one of the first signal line pair and the first power supply terminal. The sense amplifier may include a third switch configured to turn on the first switch depending on a level of the any one of the first signal line pair. The sense amplifier may include a fourth switch configured to turn on the second switch depending on a level of the other one of the first signal line pair.

Abstract: Disclosed are a polyolefin-based flame retardant resin composition and a molded product. The present invention relates to a polyolefin-based flame retardant resin composition satisfying flame retardancy (particularly, UL94V V-0, V-1, and V-2 grades, an auto ignition property of 15 seconds or less, and eco-friendly flame retardancy), improved extrusion properties, a melt index, tensile elongation, or appearance quality required in use of extruded tube molds and the like for insulation and wiring in electrical and electronic products, and vehicles using a particular phosphate-based flame retardant, and a molded product manufactured from the composition are disclosed.

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Abstract: The disclosure relates to methods of fabricating semiconductor devices. A method of fabricating a semiconductor device is provided as follows. A target layer is formed. A hard mask layer is formed on the target layer. The hard mask layer is patterned to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern. The first mask pattern encloses the plateau-shaped mask pattern. The first mask pattern is spaced apart from the plateau-shaped mask pattern. The target layer is patterned using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark. The redundant fin is removed.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A sense amplifier may be provided. The sense amplifier may include a first switch coupled between any one of a first signal line pair and a first power supply terminal. The sense amplifier may include a second switch coupled between the other one of the first signal line pair and the first power supply terminal. The sense amplifier may include a third switch configured to turn on the first switch depending on a level of the any one of the first signal line pair. The sense amplifier may include a fourth switch configured to turn on the second switch depending on a level of the other one of the first signal line pair.

Abstract: A semiconductor integrated circuit device may include a semiconductor chip, a power line region and a reservoir capacitor. The semiconductor chip may include a cell region and a peripheral circuit region. The power line region may be arranged on an edge portion of the peripheral circuit region. The reservoir capacitor may be formed on the power line region.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: The present invention relates to a combustor-independent fluidized bed indirect gasification system for technology for obtaining high quality synthetic gas through effective indirect gasification of low quality fuels, such as biomass/waste/coal, having various properties, and provides a combustor-independent fluidized bed indirect gasification system comprising: a pre-processor having a sorter 500; a gasifier 300 to which a first fuel sorted in the pre-processor is supplied; a combustor 100 to which a second fuel sorted in the pre-processor is supplied; and a riser 200 connecting the gasifier 300 and the combustor 100 and having functions of increasing the temperature of a bed material and transferring the bed material therein.