Abstract: A method of fabricating a semiconductor device is provided as follows. A target layer is formed. A hard mask layer is formed on the target layer. The hard mask layer is patterned to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern. The first mask pattern encloses the plateau-shaped mask pattern. The first mask pattern is spaced apart from the plateau-shaped mask pattern. The target layer is patterned using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark. The redundant fin is removed.

Abstract: A method of manufacturing a reticle, the method including preparing a substrate, determining position data of a pattern to be formed on the substrate, and setting a primary exposure condition to form the pattern; performing a primary exposure simulation regarding the substrate based on the position data of the pattern and the primary exposure condition; calculating a primary deformation rate of the substrate, which is generated in the primary exposure simulation; correcting the position data of the pattern based on the primary deformation rate of the substrate to provide a corrected position data of the pattern; and exposing the substrate under the primary exposure condition based on the corrected position data of the pattern.

Abstract: A semiconductor integrated circuit device may include a cell capacitor connected with any one of a first electrode and a second electrode of an access device. The cell capacitor may include a first cell cap array and a second cell cap array separated from the first cell cap array. A voltage terminal for driving the cell capacitor may be connected to a connection node between the first cell cap array and the second cell cap array.

Abstract: Disclosed are a polyolefin-based flame retardant resin composition and a molded product. The present invention relates to a polyolefin-based flame retardant resin composition satisfying flame retardancy (particularly, UL94V V-0, V-1, and V-2 grades, an auto ignition property of 15 seconds or less, and eco-friendly flame retardancy), improved extrusion properties, a melt index, tensile elongation, or appearance quality required in use of extruded tube molds and the like for insulation and wiring in electrical and electronic products, and vehicles using a particular phosphate-based flame retardant, and a molded product manufactured from the composition are disclosed.

Abstract: A semiconductor device includes a normal pad and a first monitoring unit suitable for monitoring whether a bunker is formed in the normal pad based on an inherent resistance component of the normal pad during a probe test.

Abstract: An electronic device is provided. The electronic device includes a processor, a memory configured to connect to the processor, and secure circuitry configured to connect to the processor over a physical channel receive data sent by the processor over the physical channel, and store the data.

Abstract: An electronic system may include a first circuit driven by a first power voltage signal and a first ground voltage signal, and a second circuit driven by a second power voltage signal and a second ground voltage signal. The electronic system may also include a stabilizer coupled between a first ground terminal and a second ground terminal and suitable for blocking a current flowing from the second ground terminal toward the first ground terminal.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.

Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.

Abstract: An electronic system may include a first circuit driven by a first power voltage signal and a first ground voltage signal, and a second circuit driven by a second power voltage signal and a second ground voltage signal. The electronic system may also include a stabilizer coupled between a first ground terminal and a second ground terminal and suitable for blocking a current flowing from the second ground terminal toward the first ground terminal.

Abstract: An memory device includes a bit line, an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the bit line in response to a voltage level of the bit line and a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the bit line in response to the voltage level of the bit line.

Abstract: A semiconductor device includes a normal pad and a first monitoring unit suitable for monitoring whether a bunker is formed in the normal pad based on an inherent resistance component of the normal pad during a probe test.

Abstract: A silicate phosphor composition is provided having a ?-phase of an orthorhombic crystal structure whose space group is Pbnm 62, and whose composition is represented by the following chemical formula: Ca2-x-y-zMxSiO4:yCe3+,zN(0?x<0.5,0<y?0.1,0?z<0.15) In the formula, M represents at least one member selected from the group consisting of Mg, Sr, Ba, Zn, Na, Al, Ga, Ge, P, As and Fe, and N represents at least one member selected from the group consisting of Eu2+, Mn2+, Tb3+, Yb2+ and Tm3+. The silicate phosphor has a maximum absorbance for a wavelength of about 450 nm to about 475 nm corresponding to a main part of a blue excitation light, and has a great stability at a high temperature. As such the silicate phosphor may be used in combination with a blue light source to produce a white light.

Abstract: An electrolyte for a rechargeable lithium battery includes a non-aqueous organic solvent, a lithium salt, and an additive. The additive includes a gamma butyrolactone compound substituted with at least one F atom at the ?-position.