Abstract: A method of designing a layout of a photomask and a method of manufacturing a photomask, the method of designing a layout of a photomask including obtaining a design layout of a mask pattern; performing an optical proximity correction on the design layout to obtain design data; obtaining data of a position error of a pattern occurring during an exposure of the photomask according to the design data; correcting position data of the pattern based on the position error data to correct the design data; and providing the corrected position data to an exposure device to expose an exposure beam according to the corrected design data.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.

Abstract: A method of designing a layout of a photomask and a method of manufacturing a photomask, the method of designing a layout of a photomask including obtaining a design layout of a mask pattern; performing an optical proximity correction on the design layout to obtain design data; obtaining data of a position error of a pattern occurring during an exposure of the photomask according to the design data; correcting position data of the pattern based on the position error data to correct the design data; and providing the corrected position data to an exposure device to expose an exposure beam according to the corrected design data.

Abstract: An electronic apparatus and a method for performing a settlement transaction in an electronic apparatus, according to various embodiments of the present invention, can transmit, to a settlement apparatus, settlement data, which is generated by using authentication information, in response to a settlement request inputted through the electronic apparatus; check whether a settlement response message including result information of a settlement performance using the settlement data is received; and manage stored authentication information according to whether the settlement response message is received within a predetermined time period. Also, other various embodiments are possible.

Abstract: A method of manufacturing a reticle, the method including preparing a substrate, determining position data of a pattern to be formed on the substrate, and setting a primary exposure condition to form the pattern; performing a primary exposure simulation regarding the substrate based on the position data of the pattern and the primary exposure condition; calculating a primary deformation rate of the substrate, which is generated in the primary exposure simulation; correcting the position data of the pattern based on the primary deformation rate of the substrate to provide a corrected position data of the pattern; and exposing the substrate under the primary exposure condition based on the corrected position data of the pattern.

Abstract: A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Abstract: The disclosure relates to methods of fabricating semiconductor devices. A method of fabricating a semiconductor device is provided as follows. A target layer is formed. A hard mask layer is formed on the target layer. The hard mask layer is patterned to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern. The first mask pattern encloses the plateau-shaped mask pattern. The first mask pattern is spaced apart from the plateau-shaped mask pattern. The target layer is patterned using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark. The redundant fin is removed.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A method of fabricating a semiconductor device is provided as follows. A target layer is formed. A hard mask layer is formed on the target layer. The hard mask layer is patterned to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern. The first mask pattern encloses the plateau-shaped mask pattern. The first mask pattern is spaced apart from the plateau-shaped mask pattern. The target layer is patterned using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark. The redundant fin is removed.

Abstract: A method of manufacturing a reticle, the method including preparing a substrate, determining position data of a pattern to be formed on the substrate, and setting a primary exposure condition to form the pattern; performing a primary exposure simulation regarding the substrate based on the position data of the pattern and the primary exposure condition; calculating a primary deformation rate of the substrate, which is generated in the primary exposure simulation; correcting the position data of the pattern based on the primary deformation rate of the substrate to provide a corrected position data of the pattern; and exposing the substrate under the primary exposure condition based on the corrected position data of the pattern.

Abstract: A semiconductor device includes a normal pad and a first monitoring unit suitable for monitoring whether a bunker is formed in the normal pad based on an inherent resistance component of the normal pad during a probe test.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.

Abstract: An memory device includes a bit line, an NMOS transistor configured to supply a voltage of a pull-up voltage terminal to the bit line in response to a voltage level of the bit line and a PMOS transistor configured to supply a voltage of a pull-down voltage terminal to the bit line in response to the voltage level of the bit line.

Abstract: A semiconductor device includes a normal pad and a first monitoring unit suitable for monitoring whether a bunker is formed in the normal pad based on an inherent resistance component of the normal pad during a probe test.