Patents by Inventor Jongwook Kye

Jongwook Kye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF GENERATING CIRCUIT LAYOUTS THAT ARE TO BE MANUFACTURED USING SADP ROUTING TECHNIQUES
    Publication number: 20150113484
    Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Lei Yuan, Soo Han Choi, Jongwook Kye, Harry J. Levinson
  • Middle-of-the-line constructs using diffusion contact structures
    Patent number: 9006100
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • COLOR-INSENSITIVE RULES FOR ROUTING STRUCTURES
    Publication number: 20150067633
    Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Lei YUAN, Soo Han CHOI, Li YANG, Jongwook KYE
  • Methods of generating circuit layouts that are to be manufactured using SADP techniques
    Patent number: 8966412
    Abstract: One method disclosed herein involves, among other things, identifying a plurality of features within an overall pattern layout that cannot be decomposed using the SADP process, wherein at least first and second adjacent features are required to be same-color features, decreasing a spacing between the first and second adjacent features such that the first feature and the second feature become different-color features so as to thereby render the plurality of features decomposable using the SADP process, decomposing the overall pattern layout into a mandrel mask pattern and a block mask pattern, and generating mask data sets corresponding to the mandrel mask pattern and the block mask pattern.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jongwook Kye, Harry J. Levinson
  • Interconnection designs using sidewall image transfer (SIT)
    Patent number: 8962483
    Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Youngtag Woo, Dinesh Somasekhar, Juhan Kim, Yunfei Deng, Jongwook Kye
  • Integrating optimal planar and three-dimensional semiconductor design layouts
    Patent number: 8966423
    Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye
  • Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules
    Patent number: 8954913
    Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Soo Han Choi, Jongwook Kye, Harry J. Levinson
  • METHOD FOR OFF-GRID ROUTING STRUCTURES UTILIZING SELF ALIGNED DOUBLE PATTERNING (SADP) TECHNOLOGY
    Publication number: 20150028489
    Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Lei YUAN, Jongwook KYE, Harry LEVINSON
  • Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology
    Patent number: 8921225
    Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jongwook Kye, Harry Levinson
  • FinFET device and methods of fabrication
    Patent number: 8916441
    Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan
  • Cut mask aware contact enclosure rule for grating and cut patterning solution
    Patent number: 8918746
    Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jongwook Kye, Harry J. Levinson
  • DOUBLE SIDEWALL IMAGE TRANSFER PROCESS
    Publication number: 20140353765
    Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Inventors: Youngtag WOO, Jongwook KYE, Dinesh SOMASEKHAR
  • WIDE PIN FOR IMPROVED CIRCUIT ROUTING
    Publication number: 20140353842
    Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: Lei Yuan, Juhan Kim, Jongwook Kye, Mahbub Rashed
  • FINFET DEVICE AND METHOD OF FABRICATION
    Publication number: 20140339610
    Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 20, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Jongwook Kye, Suresh Venkatesan
  • Double sidewall image transfer process
    Patent number: 8889561
    Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 18, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Youngtag Woo, Jongwook Kye, Dinesh Somasekhar
  • Methods for improving double patterning route efficiency
    Patent number: 8881083
    Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yunfei Deng, Lei Yuan, Hidekazu Yoshida, Juhan Kim, Mahbub Rashed, Jongwook Kye
  • Via insertion in integrated circuit (IC) designs
    Patent number: 8843869
    Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 23, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Lei Yuan, Jongwook Kye, Harry Levinson
  • INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT)
    Publication number: 20140273474
    Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Youngtag WOO, Dinesh Somasekhar, Juhan Kim, Yunfei Deng, Jongwook Kye
  • SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS
    Publication number: 20140264499
    Abstract: Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The semiconductor substrate also includes a conductive contact formed in the first dielectric material, the conductive contact being electrically connected to the doped region, and a dielectric cap overlying the conductive contact.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 18, 2014
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Lei Yuan, Jin Cho, Jongwook Kye
  • VIA INSERTION IN INTEGRATED CIRCUIT (IC) DESIGNS
    Publication number: 20140282345
    Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Lei YUAN, Jongwook KYE, Harry LEVINSON