Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

Abstract: A light emitting diode includes: a first conductivity type semiconductor layer; a mesa including an active layer and a second conductivity type semiconductor layer, the mesa having a groove disposed under some region of the first conductivity type semiconductor layer to expose an edge of the first conductivity type semiconductor layer, the groove exposing the first conductivity type semiconductor layer; a first electrode including a first contact portion electrically connected to the first conductivity type semiconductor layer through the groove; a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer; and an upper electrode pad disposed adjacent to the first conductivity type semiconductor layer and connected to the second electrode, wherein the groove has a shape surrounding a region including a center of the mesa and partially open.

Abstract: An organic light-emitting diode (OLED) display can include a display panel including sub-pixels; a deterioration sensing unit configured to sense a deterioration state of the display panel; a power supply configured to output a high voltage for driving the sub-pixels; and a timing controller configured to: receive a deterioration sensing result including information on the deterioration state of the display panel from the deterioration sensing unit, continuously vary the high voltage based on the deterioration sensing result received from the deterioration sensing unit, and provide the varied high voltage to the sub-pixels.

Abstract: A semiconductor light emitting device includes a first semiconductor layer, an active layer disposed on the first semiconductor layer to emit ultraviolet light, a second semiconductor layer disposed on the active layer, and a first electrode disposed on the first semiconductor layer and being in Ohmic contact with a portion of the first semiconductor layer, the first electrode including a contact electrode including aluminum (Al) and at least one other material and having a first region adjacent to the first semiconductor layer and a second region, with each region having an Al composition ratio defined by the amount of Al relative to the amount of the at least one other material. The Al composition ratio of the first region is greater than the Al composition ratio of the second region, and a metal layer disposed on the contact electrode.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A variable control method of exhaust temperature increase includes, when a cam phaser, which is connected to a double cam shaft having a coaxial arrangement structure of an outer shaft and an inner shaft, is operated and when a cam angle is determined as being varied by a controller, a cam phaser position change control is performed of decreasing a flow rate of an internal exhaust gas recirculation (EGR) supplied to a cylinder of an engine with a cam advance angle, increasing the flow rate of the EGR with a cam retard angle, or blocking the flow rate of the EGR with a maximal cam advance angle.

Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

Abstract: An OLED display device capable of preventing luminance deviation caused by a voltage drop of an EVDD is disclosed. The OLED display device generates a reference voltage, a voltage level of which varies with distance from the data driver and supplies the reference voltage to the display panel through the data driver.

Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

Abstract: In an operating method of a radio frequency integrated circuit (RFIC) including a transmission circuit and a reception circuit, the operating method includes receiving, from a modem, first information for setting transmission power of the transmission circuit or second information about a blocker which is a frequency signal unused by the RFIC, obtaining an allowable value of phase noise of a local oscillator included in the transmission circuit, using the first information, obtaining an allowable value of phase noise of a local oscillator included in the reception circuit, using the second information, determining a level of a driving voltage, using the obtained allowable values of the phase noises, and providing the driving voltage to the local oscillators.

Abstract: A light emitting diode includes: a first conductivity type semiconductor layer; a mesa including an active layer and a second conductivity type semiconductor layer, the mesa having a groove disposed under some region of the first conductivity type semiconductor layer to expose an edge of the first conductivity type semiconductor layer, the groove exposing the first conductivity type semiconductor layer; a first electrode including a first contact portion electrically connected to the first conductivity type semiconductor layer through the groove; a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer; and an upper electrode pad disposed adjacent to the first conductivity type semiconductor layer and connected to the second electrode, wherein the groove has a shape surrounding a region including a center of the mesa and partially open.

Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

Abstract: An ultraviolet light emitting diode is provided to comprise an n-type semiconductor layer disposed on a substrate; light emitting elements disposed on the n-type semiconductor layer, each comprising an active layer and a p-type semiconductor layer; an n-type ohmic contact layer contacting the n-type semiconductor layer around the micro light emitting elements; p-type ohmic contact layers contacting the p-type semiconductor layers, respectively; an n-bump electrically connecting to the n-type ohmic contact layer; and a p-bump electrically connected to the p-type ohmic contact layers, wherein each of the n-bump and the p-bump is disposed across over a plurality of micro light emitting elements. The micro light emitting elements may be arranged over a wide area of the substrate, and thus light output can be improved and a forward voltage may be lowered, in addition, the n-bump and the p-bump may be formed relatively widely.

Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality or bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

Abstract: An ultraviolet light-emitting diode includes: a substrate; an n-type semiconductor layer located on the substrate; a mesa arranged on the n-type semiconductor layer and including an active layer and a p-type semiconductor layer; an n-ohmic contact layer coming in contact with the n-type semiconductor layer; a p-ohmic contact layer coming in contact with the p-type semiconductor layer; an n-bump electrically connected to the n-ohmic contact layer; and a p-bump electrically connected to the p-ohmic contact layer, wherein the mesa includes a main branch and a plurality of sub branches extending from the main branch, the n-ohmic contact layer encompasses the mesa and is interposed in an area between the sub branches, and the n-bump and the p-bump respectively cover the upper part and sides of the mesa. Therefore, an optical output can be increased by reducing light loss, and a forward voltage can be lowered.

Abstract: A light emitting diode includes: a first conductivity type semiconductor layer; a mesa including an active layer and a second conductivity type semiconductor layer, the mesa having a groove disposed under some region of the first conductivity type semiconductor layer to expose an edge of the first conductivity type semiconductor layer, the groove exposing the first conductivity type semiconductor layer; a first electrode including a first contact portion electrically connected to the first conductivity type semiconductor layer through the groove; a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer; and an upper electrode pad disposed adjacent to the first conductivity type semiconductor layer and connected to the second electrode, wherein the groove has a shape surrounding a region including a center of the mesa and partially open.