Abstract: The present disclosure relates to a display interface device which can increase display information transmission efficiency and reduce power consumption and EMI, in which a transmission part transmits clock edge information included in a data packet of each channel at a different timing from clock edge information included in data packets of other channels. A reception part detects a clock edge of each channel from the data packet transmitted through each channel, generates an internal clock signal of each channel, synchronized with the detected clock edge, corrects a delay of each channel depending on a result of a logical operation performed on a delayed clock edge of a channel and a clock edge of another channel to further generate an internal clock signal of each channel, and restores the display information from the data packet of each channel using the internal clock signal of each channel.

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity.

Abstract: A semiconductor light emitting device includes a first semiconductor layer, an active layer disposed on the first semiconductor layer to emit ultraviolet light, a second semiconductor layer disposed on the active layer, and a first electrode disposed on the first semiconductor layer and being in Ohmic contact with a portion of the first semiconductor layer, the first electrode including a contact electrode including aluminum (Al) and at least one other material and having a first region adjacent to the first semiconductor layer and a second region, with each region having an Al composition ratio defined by the amount of Al relative to the amount of the at least one other material, wherein the Al composition ratio of the first region is greater than the Al composition ratio of the second region, and a metal layer disposed on the contact electrode.

Abstract: A light-emitting diode including a support substrate, a semiconductor stack disposed on the support substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer, a reflective metal layer disposed between the support substrate and the semiconductor stack, the reflective metal layer being in ohmic contact with the p-type compound semiconductor layer of the semiconductor stack and including a groove exposing a portion of the semiconductor stack, an insulation layer disposed between the support substrate and the semiconductor stack and disposed in the groove, and a first electrode including a first electrode pad and a first electrode extension and contacting the n-type compound semiconductor layer of the semiconductor stack, in which the first electrode extension is connected to the first electrode pad, and the first electrode extension is formed along an outer boundary of the light-emitting diode.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: A light emitting diode includes a light emitting structure including first and second conductive type semiconductor layers, an active layer, a first electrode electrically connected to the first conductive type semiconductor layer, a current blocking layer disposed on a lower surface of the light emitting structure, and a second electrode electrically connected to the second conductive type semiconductor layer. The second electrode includes a first reflective metal layer adjoining the second conductive type semiconductor layer, and a second reflective metal layer covering a lower surface of the current blocking layer and a lower surface of the first reflective metal layer, and adjoining the second conductive type semiconductor layer. A contact resistance between the second reflective metal layer and the second conductive type semiconductor layer is higher than a contact resistance between the first reflective metal layer and the second conductive type semiconductor layer.

Abstract: A display device performs efficient driving by selectively scanning a peripheral area processed to have low resolution. The display device includes a gate driver that scans a first subset of pixel rows in a first scan block including only the peripheral area during a first frame and a second frame, and respectively scan during the first frame and the second frame a second subset of pixel rows and a third subset of pixel rows in a second scan block including the medial area and the peripheral area excluding the foveal area, and scan pixel rows of pixels in a third scan block including the foveal area, the medial area, and the peripheral area during the first frame and the second frame.

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

Abstract: An exhaust heat recovery system may include a coolant circulation circuit arranged to connect an engine, an exhaust heat exchanger, a radiator, a water-cooled intercooler, and a sub-radiator, and controls each valve arranged on a passage which connects the engine, the exhaust heat exchanger, the radiator, the water-cooled intercooler, and the sub-radiator to the coolant circulation circuit according to the coolant temperature so as to control temperatures of coolant and intake air, thereby enabling the engine to be rapidly warmed up.

Abstract: A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

Abstract: A method of allocating resources in a multi-hop wireless sensor network includes (A) when two arbitrary adjacent links among links connecting all nodes have a violation relationship where the two arbitrary adjacent links occupy the same time slot, by a network coordinator node, allocating different time slots to the two arbitrary adjacent links according to a resource allocation request command message from each of nodes configuring the multi-hop wireless sensor network, (B) when two arbitrary links which are not adjacent to each other among the links are within a communication distance, by the network coordinator node, allocating different frequency channels to the two arbitrary links, and (C) when resource allocation for all of the links is completed according to steps (A) and (B), checking whether an end-to-end maximum allowable time required by each of paths established by the links is satisfied.

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity.

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure.

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity.

Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

Abstract: A light-emitting diode including a support substrate, a semiconductor stack disposed on the support substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer, a reflective metal layer disposed between the support substrate and the semiconductor stack, the reflective metal layer being in ohmic contact with the p-type compound semiconductor layer of the semiconductor stack and including a groove exposing a portion of the semiconductor stack, an insulation layer disposed between the support substrate and the semiconductor stack and disposed in the groove, and a first electrode including a first electrode pad and a first electrode extension and contacting the n-type compound semiconductor layer of the semiconductor stack, in which the first electrode extension is connected to the first electrode pad, and the first electrode extension is formed along an outer boundary of the light-emitting diode.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: A light emitting diode includes a light emitting structure including first and second conductive type semiconductor layers, an active layer, a first electrode electrically connected to the first conductive type semiconductor layer, a current blocking layer disposed on a lower surface of the light emitting structure, and a second electrode electrically connected to the second conductive type semiconductor layer. The second electrode includes a first reflective metal layer adjoining the second conductive type semiconductor layer, and a second reflective metal layer covering a lower surface of the current blocking layer and a lower surface of the first reflective metal layer, and adjoining the second conductive type semiconductor layer. A contact resistance between the second reflective metal layer and the second conductive type semiconductor layer is higher than a contact resistance between the first reflective metal layer and the second conductive type semiconductor layer.