Patents by Inventor Jordan D. Greenlee

Jordan D. Greenlee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031417
    Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
  • Publication number: 20210167020
    Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 3, 2021
    Inventors: Jordan D. Greenlee, Lifang Xu, Rita J. Klein, Xiao Li, Everett A. McTeer
  • Patent number: 11024644
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Shyam Surthi, Jordan D. Greenlee
  • Patent number: 11011408
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, Yongjun Jeff Hu
  • Publication number: 20210111064
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, Yongjun Jeff Hu
  • Publication number: 20210098028
    Abstract: Some embodiments include a method of forming a conductive structure. A metal-containing conductive material is formed over a supporting substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and to at least one oxidant. The exposure alters at least a portion of the metal-containing conductive material to thereby form at least a portion of the conductive structure. Some embodiments include a conductive structure which has a metal-containing conductive material with a first region adjacent to a second region. The first region has a greater concentration of one or both of fluorine and boron relative to the second region.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee, Peng Xu
  • Publication number: 20210098486
    Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee
  • Patent number: 10957775
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Patent number: 10943921
    Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Chet E. Carter, Collin Howder, John Mark Meldrim, Everett A. McTeer
  • Publication number: 20210066332
    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
    Type: Application
    Filed: October 15, 2020
    Publication date: March 4, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
  • Publication number: 20210057440
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 25, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Daniel Billingsley, Indra V. Chary, Rita J. Klein
  • Publication number: 20210057438
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Shyam Surthi, Jordan D. Greenlee
  • Publication number: 20210050361
    Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material than may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Inventors: John D. Hopkins, Rita J. Klein, Jordan D. Greenlee
  • Publication number: 20210005732
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Applicant: Micron Technology, Inc.
    Inventors: David Ross Economy, Rita J. Klein, Jordan D. Greenlee, John Mark Meldrim, Brenda D. Kraus, Everett A. McTeer
  • Publication number: 20200402993
    Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 24, 2020
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin D. Shepherdson, Collin Howder, Jordan D. Greenlee
  • Patent number: 10847367
    Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David R. Economy, Brian Beatty, John Mark Meldrim, Yongjun Jeff Hu, Jordan D. Greenlee
  • Patent number: 10840255
    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
  • Publication number: 20200350333
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
  • Publication number: 20200328348
    Abstract: Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 15, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Tao D. Nguyen, John Mark Meldrim, Aaron K. Belsher
  • Publication number: 20200328284
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 15, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John Mark Meldrim