Patents by Inventor Jordan D. Greenlee

Jordan D. Greenlee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071495
    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs having insulative material atop treads of the stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Conductive vias extend through the insulative material. Individual of the conductive vias are directly above and directly against the conducting material of the respective individual tread. A lining is over sidewalls of the individual conductive vias. The lining has a bottom. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Jiewei Chen, Jordan D. Greenlee, Shuangqiang Luo, Silvia Borsari
  • Publication number: 20240071502
    Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Alyssa N. Scarbrough, Lifang Xu, Jordan D. Greenlee
  • Publication number: 20240071816
    Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Alyssa N. Scarbrough, Lifang Xu, Jordan D. Greenlee
  • Publication number: 20240074179
    Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of individual of the channel-material strings is directly electrically coupled to the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises a pair of side interfaces that individually extend downwardly from a top of the conductor tier on one of opposing sides of the intervening material and individually extend longitudinally-along the immediately-laterally-adjacent memory blocks.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc
    Inventors: John D. Hopkins, Damir Fazil, Jordan D. Greenlee
  • Patent number: 11910606
    Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee
  • Patent number: 11910596
    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Alyssa N. Scarbrough, John D. Hopkins
  • Publication number: 20240057335
    Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 15, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins
  • Patent number: 11894305
    Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 6, 2024
    Inventors: Jordan D. Greenlee, John D. Hopkins, Rita J. Klein, Everett A. McTeer, Lifang Xu, Daniel Billingsley, Collin Howder
  • Patent number: 11895835
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an tipper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the tipper and lower polysilicon-comprising layers.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Alyssa N. Scarbrough, Jordan D. Greenlee, John D. Hopkins
  • Patent number: 11895834
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jiewei Chen, Jordan D. Greenlee, Mithun Kumar Ramasahayam, Nancy M. Lomeli
  • Publication number: 20240032295
    Abstract: Electronic devices comprising a source stack comprising one or more conductive materials, a source contact adjacent to the source stack, tiers of alternating conductive materials and insulative materials adjacent to the source contact, pillars extending through the tiers and the source contact and into the source stack, a slit structure extending through the tiers and the source contact, and an implant structure extending within the slit structure and into the source stack. Related methods and systems are also disclosed.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 25, 2024
    Inventors: John D. Hopkins, Jordan D. Greenlee
  • Publication number: 20230422503
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, John D. Hopkins, Yongjun Jeff Hu, Swapnil Lengade
  • Patent number: 11856764
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins
  • Publication number: 20230397418
    Abstract: A microelectronic device comprises lateral contact structures overlying a source structure and comprising conductive material, a cap material overlying the lateral contact structures and comprising implant regions therein, a stack structure overlying the cap material and comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers, and pillars vertically extending through the stack structure and into the source structure. The pillars individually comprise semiconductive channel material in physical contact with the lateral contact structures. The microelectronic device comprises filled slot structures vertically extending at least through the stack structure and the cap material. The filled slot structures are positioned within horizontal areas of the implant regions of the cap material. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Zhiqiang Teo, Chun Wei Ee, Anson Lin, Yuwei Ma, Martin J. Barclay, John D. Hopking, Jordan D. Greenlee
  • Publication number: 20230395149
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 7, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, David Ross Economy, John D. Hopkins, Nancy M. Lomeli, Jiewei Chen, Rita J. Klein, Everett A. McTeer, Aaron P. Thurber
  • Publication number: 20230397420
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings extend through the first tiers and the second tier. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli, Jordan D. Greenlee
  • Publication number: 20230395507
    Abstract: A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 7, 2023
    Inventors: Xiao Li, Jordan D. Greenlee
  • Publication number: 20230395510
    Abstract: Microelectronic devices include a stack with a vertically alternating sequence of insulative and conductive structures arranged in tiers. A staircased stadium within the stack comprises steps at different tier elevations of a group of the tiers. Treads of the steps are each provided by an upper surface area of one of the conductive structures within the group of the tiers and by an upper surface area of a metal oxide region extending through the one of the conductive structures. A pair of conductive contact structures extends to one of the steps. A first conductive contact structure of the pair terminates at the tread of the step, within the area of the conductive structure. A second conductive contact structure of the pair extends through the tread of the step, within the upper surface area of the metal oxide region. Related fabrication methods and electronic systems are also disclosed.
    Type: Application
    Filed: July 12, 2022
    Publication date: December 7, 2023
    Inventors: Mithun Kumar Ramasahayam, Jordan D. Greenlee, Harsh Narendrakumar Jain, Jiewei Chen, Indra V. Chary
  • Publication number: 20230397424
    Abstract: A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.
    Type: Application
    Filed: May 25, 2023
    Publication date: December 7, 2023
    Inventors: Jordan D. Greenlee, Everett A. McTeer, Rita J. Klein, John D. Hopkins, Nancy M. Lomeli, Xiao Li, Christopher R. Ritchie, Alyssa N. Scarbrough, Jiewei Chen, Sijia Yu, Naiming Liu
  • Publication number: 20230395704
    Abstract: Methods, systems, and devices for self-aligned etching techniques for memory formation are described. A memory device may include a stack of alternating materials and a pillar extending through the stack of alternating materials, where the stack of alternating materials and the pillar may form a set of multiple memory cells. A polysilicon material may be formed above the pillar, where the polysilicon material may be associated with a selector device for the memory cells. A masking material may be formed above the polysilicon material and the stack of alternating materials, where the masking material may be aligned with the polysilicon material and may have a width that is greater than a width of the polysilicon material and the pillar. The masking material may prevent the polysilicon material, the pillar, and a portion of the stack of alternating materials beneath the masking material from being removed during an etching operation.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: John Hopkins, Jordan D. Greenlee