Patents by Inventor Joseph C. Sher
Joseph C. Sher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11093588Abstract: Data obfuscation is generally discussed herein. In one or more embodiments, a memory circuit can include a storage portion including entries with corresponding addresses, one or more of the entries configured to include data stored thereon, and processing circuitry to read first data from a first entry of the entries, alter the first data by at least one of: (1) flipping one or more bits of the first data, (2) scrambling two or more bits of the first data, and (3) altering an address of the first data, and write the altered first data to the storage portion.Type: GrantFiled: June 26, 2017Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Donald M. Morgan, Joseph C. Sher
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Publication number: 20180373850Abstract: Data obfuscation is generally discussed herein. In one or more embodiments, a memory circuit can include a storage portion including entries with corresponding addresses, one or more of the entries configured to include data stored thereon, and processing circuitry to read first data from a first entry of the entries, alter the first data by at least one of: (1) flipping one or more bits of the first data, (2) scrambling two or more bits of the first data, and (3) altering an address of the first data, and write the altered first data to the storage portion.Type: ApplicationFiled: June 26, 2017Publication date: December 27, 2018Inventors: Donald M. Morgan, Joseph C. Sher
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Patent number: 7468623Abstract: A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage after certification of the semiconductor device. The operational supply voltage is lower than the test supply voltage. The voltage control circuit includes a clamp circuit having a plurality of voltage regulation devices, typically diodes. The voltage regulation devices control an output of the clamp circuit. A voltage regulator is electrically coupled to the clamp circuit and generates a first control signal based upon the output of the clamp circuit. A charge pump then receives the control signal from the voltage regulator, and, based on the value of the control signal, the charge pump generates the test supply voltage. At least one bypass device is connected to at least one of the plurality of voltage regulation devices. The bypass device is activated following the certification of the semiconductor device.Type: GrantFiled: November 19, 2001Date of Patent: December 23, 2008Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, Daniel R. Loughmiller
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Patent number: 6946863Abstract: A method for passing a voltage between an internal node inside a memory device and an external pin outside the memory device. The method includes passing an internal voltage from the internal node to the external pin during a read mode. The method also includes passing an external voltage from the external pin to the internal node during a force mode.Type: GrantFiled: August 7, 2000Date of Patent: September 20, 2005Assignee: Micron Technology, Inc.Inventors: Daniel R. Loughmiller, Joseph C. Sher, Kevin G. Duesman
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Patent number: 6930503Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: GrantFiled: April 30, 2004Date of Patent: August 16, 2005Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Patent number: 6885238Abstract: A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage after certification of the semiconductor device. The operational supply voltage is lower than the test supply voltage. The voltage control circuit includes a clamp circuit having a plurality of voltage regulation devices, typically diodes. The voltage regulation devices control an output of the clamp circuit. A voltage regulator is electrically coupled to the clamp circuit and generates a first control signal based upon the output of the clamp circuit. A charge pump then receives the control signal from the voltage regulator, and, based on the value of the control signal, the charge pump generates the test supply voltage. At least one bypass device is connected to at least one of the plurality of voltage regulation devices. The bypass device is activated following the certification of the semiconductor device.Type: GrantFiled: June 9, 2003Date of Patent: April 26, 2005Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, Daniel R. Loughmiller
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Publication number: 20040201399Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: ApplicationFiled: April 30, 2004Publication date: October 14, 2004Applicant: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Patent number: 6756805Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: GrantFiled: November 15, 2002Date of Patent: June 29, 2004Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Publication number: 20040027190Abstract: A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage after certification of the semiconductor device. The operational supply voltage is lower than the test supply voltage. The voltage control circuit includes a clamp circuit having a plurality of voltage regulation devices, typically diodes. The voltage regulation devices control an output of the clamp circuit. A voltage regulator is electrically coupled to the clamp circuit and generates a first control signal based upon the output of the clamp circuit. A charge pump then receives the control signal from the voltage regulator, and, based on the value of the control signal, the charge pump generates the test supply voltage. At least one bypass device is connected to at least one of the plurality of voltage regulation devices. The bypass device is activated following the certification of the semiconductor device.Type: ApplicationFiled: June 9, 2003Publication date: February 12, 2004Inventors: Joseph C. Sher, Daniel R. Loughmiller
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Patent number: 6633196Abstract: An integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.Type: GrantFiled: July 8, 2002Date of Patent: October 14, 2003Assignee: Micron Technology, Inc.Inventor: Joseph C. Sher
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Patent number: 6586290Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.Type: GrantFiled: June 15, 1998Date of Patent: July 1, 2003Assignee: Micron Technology, Inc.Inventors: Stephen L. Casper, Manny K. F. Ma, Joseph C. Sher
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Publication number: 20030090285Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: ApplicationFiled: November 15, 2002Publication date: May 15, 2003Applicant: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Patent number: 6507235Abstract: A method is disclosed wherein the voltage of a semiconducting substrate can be locally pumped to a voltage different than the bulk of the semiconducting substrate generally. The local voltage may be pumped into a localized portion of the bulk substrate, or it may be pumped into a portion of the substrate that is isolated from the bulk substrate. This localized biasing may be used for various purposes, including the adjustment of body effect in a plurality of transistors, adjusting the threshold voltage of a capacitor, and reducing latch-up sensitivity of a transistor circuit.Type: GrantFiled: June 18, 1996Date of Patent: January 14, 2003Assignee: Micron Technology, Inc.Inventor: Joseph C. Sher
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Patent number: 6507074Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.Type: GrantFiled: August 30, 2001Date of Patent: January 14, 2003Assignee: Micron Technology, Inc.Inventors: Stephen L. Casper, Manny K. F. Ma, Joseph C. Sher
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Patent number: 6504396Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.Type: GrantFiled: September 17, 2001Date of Patent: January 7, 2003Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, Manny K. F. Ma
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Patent number: 6496027Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.Type: GrantFiled: August 21, 1997Date of Patent: December 17, 2002Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
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Publication number: 20020175741Abstract: An integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.Type: ApplicationFiled: July 8, 2002Publication date: November 28, 2002Inventor: Joseph C. Sher
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Patent number: 6449207Abstract: A fuse or antifuse reading circuit for accurately reading the conductive state of a marginally blown fuse or antifuse in spite of an increasing internal voltage supply. The antifuse reading circuit includes a voltage divider circuit to produce a fuse power supply that has a proportional relationship to the internal voltage supply. The antifuse reading circuit further includes a latch that receives the fuse power supply and produces an output signal indicative of the conductive state of the fuse or antifuse. The latch is set when the fuse or antifuse is not conductive and reset by a latch control circuit when the fuse or antifuse is conductive. The latch control circuit has a variable resistance to compensate for an increasing internal voltage supply. The variable resistance is controlled by a signal with an output level having a proportional relationship to the internal voltage supply that is greater than that for the fuse power supply.Type: GrantFiled: June 1, 2001Date of Patent: September 10, 2002Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, Nick VanHeel
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Patent number: 6445644Abstract: A clock generator which provides a stable, programmable pulse width output clock signal based on an input clock signal. The clock generator provides a leading edge of an output clock signal in response to a leading edge of an input clock signal. The trailing edge of the output clock signal is conditioned on feedback of the leading edge output clock signal with the trailing edge of the input signal.Type: GrantFiled: December 21, 2000Date of Patent: September 3, 2002Assignee: Micron Technology, Inc.Inventor: Joseph C. Sher
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Patent number: 6417721Abstract: An inventive integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.Type: GrantFiled: June 11, 2001Date of Patent: July 9, 2002Assignee: Micron Technology, Inc.Inventor: Joseph C. Sher