Abstract: A ring oscillator composed of a plurality of series connected inverters, the number of which may be varied after fabrication of the ring oscillator by selectively programming selections between the output of the ring oscillator and the inputs of respective inverters. In the preferred embodiment of the invention, a logic gate receiving an enable signal is connected in series with the inverters to allow the ring oscillator to be selectively enabled. Programmable connections, such as laser fuses, metal fuses, or semiconductor switches, are connected between the output of the ring oscillator and the inputs of at least some of the inverters. The ring oscillator may be advantageously used to drive the voltage pump used in a conventional DRAM integrated circuit. The inventive ring oscillator may also be used to periodically trigger a refresh circuit in a DRAM integrated circuit.

Abstract: A self-timing antifuse programming controller optimizes programming of one or many antifuses. A programming current through the antifuse is monitored until it reaches a current trip point, thereby initiating a delay period. The delay period is determined by charging a capacitor with a scaled replicate of the antifuse current until a trip point voltage is reached. Antifuses which are more resistive receive a longer programming time. The current trip point and delay period are independently programmable. The antifuse programming controller also flags completion of antifuse programming allowing expeditious programming of further antifuses in an array of antifuses to minimize overall programming time.

Abstract: A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points.

Abstract: A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

Abstract: A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points.

Abstract: An improved power-up circuit formed in an integrated circuit for generating a power-up pulse for integrated circuit devices. The present invention includes an input stage, an output stage, and a pulse control circuit. The input stage receives a supply voltage rising from a reference ground to a steady supply voltage upon power-up. The input stage generates a logic low state for a selected period of time, and a logic high state thereafter. An output stage is connected to the input stage, and generates a logic high state when the input stage is generating the logic low state. The output stage switches to the logic low state when the input stage switches to the logic high state after the selected time period. The logic high and low states sequentially generated by the output stage define the power-up pulse. The pulse control circuit is connected between the input and output of the output stage for controlling the width of the power-up pulse.