Abstract: A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points.

Abstract: A super-voltage circuit with a fast reset capability is formed in an integrated circuit for generating a test mode logic state for testing other circuits in the same integrated circuit. The super-voltage circuit includes a sensing circuit, a reset circuit, and an output circuit connected to both the sensing circuit and the reset circuit. When the input voltage receives a super-voltage which is higher than either the logic high or low voltages, the sensing circuit generates at its output a high voltage. The reset circuit also receiving the same input voltage as the sensing circuit generates at its output a logic low state when the input voltage is at the super-voltage or logic high voltage. When the sensing circuit is generating the high voltage and the reset circuit is generating the logic low state the output circuit generates at its output a logic low voltage. The logic low voltage signifies that the integrated circuit is now in the super-voltage test mode.

Abstract: A test circuit for stress testing antifuses before programming. The test circuit provides a voltage to an antifuse detection circuit during antifuse stress testing. In one embodiment, the provided voltage is externally received at a probe pad. In another embodiment, the test circuit controls a voltage generating circuit output voltage from a normal operating voltage to a stress voltage, such as by shifting the ground reference for the voltage generating circuit. The stress voltage can be varied as needed for a particular test setup and/or for different batches of antifuse circuits. Since the stress voltage is independent of the power supply voltage VCC, antifuse stressing can be concurrent with other pre-fuse tests, obviating the need for a dedicated antifuse stress test and reducing test time.

Abstract: A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one version, the circuit (110) involves a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) provides a measurement of the voltage at the node (114) as an output to a pin (116). A reset circuit (122) is coupled to the pass circuit (118) and is operable to activate and reset the pass circuit (118). Finally, a pass control circuit (120) is coupled to provide an output signal to the pass circuit (118) that drives the pass circuit (118) when active to pass the voltage at the node (114) to the pin (116).

Abstract: Connection of a reference voltage to an inverter of an input buffer is controlled to protect the buffer from damage due to high voltage connected to the buffer so that the inverter is isolated from the reference voltage for application of the high voltage. A supply voltage may be connected to the inverter to ensure the output state of the buffer when the inverter is isolated from the reference voltage. In particular, an input buffer including an inverter having at least one p-channel and at least two n-channel transistors connected in series between a supply voltage and a reference voltage is protected from damage due to high voltage by floating the source and drain of n-channel transistors connected to receive input signals to be buffered. A control signal indicating a high voltage is connected to the buffer turns off the last n-channel transistor in the series chain of transistors and thereby removes the reference voltage from any remaining n-channel transistors in the chain.

Abstract: In an integrated circuit including test circuitry for testing integrated circuit function, a programmable supervoltage circuit is described for enabling the test circuitry. The supervoltage circuit includes a reference circuit, a step-down circuit, a sensing circuit, and an output circuit. The reference circuit produces a reference voltage. The step-down circuit receives an input voltage and produces a stepped-down voltage. The sensing circuit is coupled with the reference and step-down circuits, receives the reference and stepped-down voltages, and produces a sense signal as a function of the relative values of the reference and stepped-down voltages. The output circuit is coupled with the sensing circuit, receives the sense signal, and produces a supervoltage output signal to enable the test circuitry.

Abstract: An output driver circuit that compensates for variations in supply voltage to provide more consistent switching speed characteristics. In one embodiment, the output driver circuit includes a plurality of pull down devices which are connected in parallel with one another between an output node of the circuit and ground. One of the pull down devices is coupled to a source of a pull down signal to be turned on in response to the pull down signal. The other pull down devices are turned on selectively, depending upon the level of the supply voltage. The lower the supply voltage, the more pull down devices that are turned on. A latch is provided at the input of each of the pull down devices. The result of the selective enabling of the pull down devices is that a more uniform pull down speed is provided for different levels of the supply voltage.

Abstract: An inventive integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

Abstract: A programming circuit for an anti-fuse utilizes a boot circuit that charges a capacitor to the supply voltage during a non-programming period. Anti-fuse is to be programmed, the plate of the capacitor to which the supply voltage has been applied is switched to 0 volts, thereby causing the other plate of the capacitor to output a negative voltage. This negative voltage is switched to one plate of an anti-fuse, and the other plate of the anti-fuse receives a positive voltage from an external source. A voltage is thereby applied across the anti-fuse that is greater than any voltage applied to any node of the integrated circuit.

Abstract: A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

Abstract: A test circuit for stress testing antifuses before programming. The test circuit provides a voltage to an antifuse detection circuit during antifuse stress testing. In one embodiment, the provided voltage is externally received at a probe pad. In another embodiment, the test circuit controls a voltage generating circuit output voltage from a normal operating voltage to a stress voltage, such as by shifting the ground reference for the voltage generating circuit. The stress voltage can be varied as needed for a particular test setup and/or for different batches of antifuse circuits. Since the stress voltage is independent of the power supply voltage VCC, antifuse stressing can be concurrent with other pre-fuse tests, obviating the need for a dedicated antifuse stress test and reducing test time.

Abstract: A programming circuit programs an anti-fuse having first and second terminals with the programming circuit and the anti-fuse being fabricated in the same integrated circuit. The programming circuit includes a first external terminal of the integrated circuit coupled to the first terminal of the anti-fuse. The first external terminal is adapted to receive a first programming voltage having a predetermined polarity. A second external terminal of the integrated circuit is adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage. A voltage translation circuit is coupled between the second external terminal and the second terminal of the anti-fuse and includes an enable terminal adapted to receive an enable signal. The voltage translation circuit is operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active.

Abstract: A supervoltage circuit has been described which uses a resistor divider as an input stage. The resistor divider decreases the dependancy of the supervoltage trip point on transistor threshold voltages (Vt). The stability of supervoltage trip point is significantly increased over traditional supervoltage circuits using diode connected transistors as an input stage. The supervoltage circuit can be included in any integrated circuit including memory devices.

Abstract: A self-timing antifuse programming controller optimizes programming of one or many antifuses. A programming current through the antifuse is monitored until it reaches a current trip point, thereby initiating a delay period. The delay period is determined by charging a capacitor with a scaled replicate of the antifuse current until a trip point voltage is reached. Antifuses which are more resistive receive a longer programming time. The current trip point and delay period are independently programmable. The antifuse programming controller also flags completion of antifuse programming allowing expeditious programming of further antifuses in an array of antifuses to minimize overall programming time.

Abstract: An output driver circuit that compensates for variations in supply voltage to provide more consistent switching speed characteristics. In one embodiment, the output driver circuit includes a plurality of pull down devices which are connected in parallel with one another between an output node of the circuit and ground. One of the pull down devices is coupled to a source of a pull down signal to be turned on in response to the pull down signal. The other pull down devices are turned on selectively, depending upon the level of the supply voltage. The lower the supply voltage, the more pull down devices that are turned on. A latch is provided at the input of each of the pull down devices. The result of the selective enabling of the pull down devices is that a more uniform pull down speed is provided for different levels of the supply voltage.

Abstract: A method and apparatus for increasing the number of contacts provided between two conductive layers separated by an insulator in a semiconductor integrated circuit chip is disclosed. In a first row of contacts, each contact in the row is separated by a distance, L. A second row of contacts is formed parallel to the first row. Each contact in the second row is spaced a distance of L from other contacts in the row. However, the second row is staggered from the first row, such that each contact is halfway between adjacent contacts in the first row. Each contact in the second row is located a distance of L from the two closest contacts in the first row. Successive rows are formed in a similar staggered manner.

Abstract: Circuitry in an integrated circuit for programming an antifuse element is disclosed. In one embodiment, oscillating voltages are produced at two nodes, and these voltages are approximately 180.degree. out of phase with one another. In another embodiment, an oscillating voltage is produced at one node and a negative voltage is produced at a second node. In each embodiment, the maximum difference in voltage between the two nodes is sufficient to program an antifuse element.

Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

Abstract: A super-voltage circuit with a fast reset capability is formed in an integrated circuit for generating a test mode logic state for testing other circuits in the same integrated circuit. The super-voltage circuit includes a sensing circuit, a reset circuit, and an output circuit connected to both the sensing circuit and the reset circuit. When the input voltage receives a super-voltage which is higher than either the logic high or low voltages, the sensing circuit generates at its output a high voltage. The reset circuit also receiving the same input voltage as the sensing circuit generates at its output a logic low state when the input voltage is at the super-voltage or logic high voltage. When the sensing circuit is generating the high voltage and the reset circuit is generating the logic low state, the output circuit generates at its output a logic low voltage. The logic low voltage signifies that the integrated circuit is now in the super-voltage test mode.

Abstract: An improved power-up circuit formed in an integrated circuit for generating a power-up pulse for integrated circuit devices. The present invention includes an input stage, an output stage, and a pulse control circuit. The input stage receives a supply voltage rising from a reference ground to a steady supply voltage upon power-up. The input stage generates a logic low state for a selected period of time, and a logic high state thereafter. An output stage is connected to the input stage, and generates a logic high state when the input stage is generating the logic low state. The output stage switches to the logic low state when the input stage switches to the logic high state after the selected time period. The logic high and low states sequentially generated by the output stage define the power-up pulse. The pulse control circuit is connected between the input and output of the output stage for controlling the width of the power-up pulse.