Patents by Inventor Joseph F. Brooks

Joseph F. Brooks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100171088
    Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.
    Type: Application
    Filed: March 16, 2010
    Publication date: July 8, 2010
    Inventors: Kristy A. Campbell, Jon Daley, Joseph F. Brooks
  • Patent number: 7709289
    Abstract: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of the stack includes a resistance variable material. The method also includes forming a first conductive layer on the stack and etching the conductive layer and at least one of the layers of the stack to form a first pattern of material stacks. The etched first conductive layer forming a plurality of second electrodes with a portion of the resistance variable material located between each of the first and second electrodes.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: May 4, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jon Daley, Joseph F. Brooks
  • Patent number: 7709885
    Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: May 4, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jon Daley, Kristy A. Campbell, Joseph F. Brooks
  • Patent number: 7701760
    Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, Jon Daley, Joseph F. Brooks
  • Patent number: 7691683
    Abstract: Electrode structures, variable resistance memory devices, and methods of making the same, which minimize electrode work function variation. Methods of forming an electrode having a minimized work function variation include methods of eliminating concentric circles of material having different work functions. Exemplary electrodes include electrode structures having concentric circles of materials with different work functions, wherein this difference in workfunction has been minimized by recessing these materials within an opening in a dielectric and forming a third conductor, having a uniform work function, over said recessed materials.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: April 6, 2010
    Inventors: Joseph F. Brooks, John T. Moore
  • Patent number: 7663133
    Abstract: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of the stack includes a resistance variable material. The method also includes forming a first conductive layer on the stack and etching the conductive layer and at least one of the layers of the stack to form a first pattern of material stacks. The etched first conductive layer forming a plurality of second electrodes with a portion of the resistance variable material located between each of the first and second electrodes.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jon Daley, Joseph F. Brooks
  • Patent number: 7619247
    Abstract: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the at least one second memory elements.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: November 17, 2009
    Assignee: Micron Technology, Inc.
    Inventors: John Moore, Kristy A. Campbell, Joseph F. Brooks
  • Patent number: 7579615
    Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: August 25, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Jon Daley, Kristy A. Campbell, Joseph F. Brooks
  • Patent number: 7542319
    Abstract: The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a constant current device that maintains a constant current over an applied voltage range of at least approximately 700 mV. The invention also provides a method of changing and resetting the constant current value in a constant current device by either applying a positive potential to decrease the constant current value, or by applying a voltage more negative than the existing constant current's voltage upper limit, thereby resetting or increasing its constant current level to its original fabricated value. The invention further provides a method of forming and converting a memory device into a constant current device. The invention also provides a method for using a constant current device as an analog memory device.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 2, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, Terry L. Gilton, John T. Moore, Joseph F. Brooks
  • Publication number: 20090078925
    Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 26, 2009
    Inventors: Kristy A. Campbell, Jon Daley, Joseph F. Brooks
  • Patent number: 7485948
    Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: February 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: John Moore, Joseph F. Brooks
  • Publication number: 20080299701
    Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
    Type: Application
    Filed: July 29, 2008
    Publication date: December 4, 2008
    Inventors: John Moore, Joseph F. Brooks
  • Patent number: 7459336
    Abstract: Embodiments of the invention provide a method of forming a chalcogenide material containing device, and particularly resistance variable memory elements. A stack of one or more layers is formed over a substrate. The stack includes a layer of chalcogenide material and a metal, e.g., silver, containing layer. A protective layer is formed over the stack. The protective layer blocks light, is conductive, and is etch able with the other layers of the stack. Further, the metal of the metal containing layer is substantially insoluble in the protective layer. The stack and the protective layer are then patterned and etched to form memory elements.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: December 2, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Joseph F. Brooks
  • Patent number: 7433227
    Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: October 7, 2008
    Assignee: Micron Technolohy, Inc.
    Inventors: Kristy A. Campbell, Jon Daley, Joseph F. Brooks
  • Patent number: 7344946
    Abstract: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the at least one second memory elements.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 18, 2008
    Assignee: Micron Technology, Inc.
    Inventors: John Moore, Kristy A. Campbell, Joseph F. Brooks
  • Patent number: 7332401
    Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: February 19, 2008
    Assignee: Micron Technology, Ing.
    Inventors: John T. Moore, Joseph F. Brooks
  • Patent number: 7315465
    Abstract: The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a constant current device that maintains a constant current over an applied voltage range of at least approximately 700 mV. The invention also provides a method of changing and resetting the constant current value in a constant current device by either applying a positive potential to decrease the constant current value, or by applying a voltage more negative than the existing constant current's voltage upper limit, thereby resetting or increasing its constant current level to its original fabricated value. The invention further provides a method of forming and converting a memory device into a constant current device. The invention also provides a method for using a constant current device as an analog memory device.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: January 1, 2008
    Assignee: Micro Technology, Inc.
    Inventors: Kristy A. Campbell, Terry L. Gilton, John T. Moore, Joseph F. Brooks
  • Patent number: 7289349
    Abstract: A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a low resistance state upon application of a voltage and, when the voltage is removed, to re-assume the high resistance state. Additionally, the threshold device can be configured to switch in response to both negative and positive applied voltages across the first and second electrodes. Memory elements having a memory portion and threshold device between first and second electrodes and methods for forming the memory elements are also provided.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: October 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, Jon Daley, Joseph F. Brooks
  • Patent number: 7288784
    Abstract: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the at least one second memory elements.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: October 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: John Moore, Kristy A. Campbell, Joseph F. Brooks
  • Patent number: 7277313
    Abstract: A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a low resistance state upon application of a voltage and, when the voltage is removed, to re-assume the high resistance state. Additionally, the threshold device can be configured to switch in response to both negative and positive applied voltages across the first and second electrodes. Memory elements having a memory portion and threshold device between first and second electrodes and methods for forming the memory elements are also provided.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, Jon Daley, Joseph F. Brooks