Access transistor for memory device

- Micron Technology, Inc.

An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

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Description
FIELD OF THE INVENTION

The invention relates to the field of random access memory (RAM) devices formed using a resistance variable material.

BACKGROUND OF THE INVENTION

Resistance variable memory elements, which include memory elements using chalcogenide glasses, have been investigated for suitability as semi-volatile and non-volatile random access memory devices. An exemplary chalcogenide resistance variable memory element is disclosed in U.S. Pat. No. 6,867,064 to Campbell et al.

In a typical chalcogenide resistance variable memory element, a conductive material, for example, silver or copper, is incorporated into a chalcogenide glass. The resistance of the chalcogenide glass can be programmed to stable higher resistance and lower resistance states. An unprogrammed chalcogenide variable resistance memory element is normally in a higher resistance state. A write operation programs the element to a lower resistance state by applying a voltage potential across the chalcogenide glass and forming a conductive pathway therein. The element may then be read by applying a voltage pulse of a lesser magnitude than the magnitude required to program the element; the resistance across the memory device is then sensed as higher or lower to define two logic states.

The programmed lower resistance state of a chalcogenide variable resistance element can remain intact for an indefinite period, typically ranging from hours to weeks, after the voltage potentials are removed; however, some refreshing may be useful. The element can be returned to its higher resistance state by applying a reverse voltage potential of about the same order of magnitude as used to write the device to the lower resistance state. Again, the higher resistance state is maintained in a semi- or non-volatile manner once the voltage potential is removed. In this way, such an element can function as a semi- or non-volatile variable resistance memory having at least two resistance states, which can define two respective logic states, i.e., at least a bit of data.

FIG. 1 illustrates an exemplary construction of a resistance variable memory element 10 and an access transistor 83, as described in U.S. Pat. No. 6,867,064. The memory element 10 is fabricated over a semiconductor substrate 62 and comprises a first insulating layer 60 formed over the substrate 62. The insulating layer 60 contains a conductive plug 61. A first metal electrode 52 is formed within a second insulating layer 53 provided over the insulating layer 60 and plug 61. A third insulating layer 68 is formed over the first electrode 52 and second insulating layer 53. A chalcogenide glass layer 58 is within the third insulating layer 68. A metal, such as silver, is incorporated into the chalcogenide glass layer 58.

As shown in FIG. 1, the first electrode 52 is electrically connected to a source/drain region 81 of an access transistor 83, which is fabricated within and on the substrate 62. Another source/drain region 85 is connected by a bit line plug 87 to a bit line of a memory array. For purposes of clarity, the bit lines and word lines are not shown in FIG. 1. The gate of the transistor 83 is part of a word line which is connected to a plurality of resistance variable memory elements just as a bit line (not shown) may be coupled to a plurality of resistance variable memory elements through respective access transistors. The bit line may be formed over a fourth insulating layer (not shown) and connects to the bit line plug 87, which in turn connects to access transistor 83 as described above.

One of the limiting factors in increasing the density of a memory device array is the amount of substrate 62 surface area used to form each memory element 10 and associated devices, such as the access transistor 83. In the industry terminology, the surface area required for a memory cell is characterized in terms of the minimum feature size “F” that is obtainable by the lithography technology used to form the memory cell. As shown in FIG. 1, the conventional memory element 10 is laid out with an access transistor 83 that includes first and second source/drain regions 83, 85 that are disposed horizontally along the substrate 62 surface. When isolation between adjacent transistors is considered, the surface area required for such a transistor is generally 8F2 or 6F2.

Accordingly, there is a need in the art for resistance variable memory devices having more efficient use of substrate surface.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the invention include an access transistor for a resistance variable memory element and methods of forming the same. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with and located below at least one resistance variable memory element.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which:

FIG. 1 depicts a resistance variable memory element and access transistor;

FIG. 2A illustrates a portion of a memory array including an access transistor according to an exemplary embodiment of the invention;

FIGS. 2B and 2C are top down views of the array of FIG. 2A;

FIGS. 3A-3J depict the formation of the memory elements of FIGS. 2A-2C at different stages of processing; and

FIG. 4 is a block diagram of a system including a memory element according to an exemplary embodiment of the invention.

 DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to various specific embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be employed, and that various structural, logical and electrical changes may be made without departing from the spirit or scope of the invention.

The term “substrate” used in the following description may include any supporting structure including, but not limited to, a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a semiconductor substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. The substrate need not be semiconductor-based, but may be any support structure suitable for supporting an integrated circuit, including, but not limited to, metals, alloys, glasses, polymers, ceramics, and any other supportive materials as is known in the art.

The invention is now explained with reference to the figures, which illustrate exemplary embodiments and throughout which like reference numbers indicate like features. FIG. 2A depicts a portion of a memory array 100 according to an exemplary embodiment of the invention. Specifically, FIG. 2A shows two memory elements 135, each memory element 135 being associated with a respective access transistor 110. Each memory element 135 is at least over at least a portion of the respective access transistor 135. The memory elements 135 and access transistors 110 are supported by a substrate 101. It should be understood, however, that the array 100 can include additional memory elements 135 each electrically connected to at least one access transistor 110.

Over the substrate 101 is a first dielectric region 119. Digit lines 111 are formed over the first dielectric region 119. The digit lines 111 are, for example, tungsten, but other conductive materials can be used. One or more dielectric layers form a second dielectric region 120 over and on lateral sides of the digit lines 111. Word lines 112 (see also FIGS. 2B and 2C) overlie the second dielectric region 120. Like the digit lines 111, the word lines 112 may be formed of tungsten, but other conductive materials can be used. There is an insulating layer 118 over and in contact with each word lines 112. A third dielectric region 121 having one or more dielectric layers is over the word lines 112 and insulating layers 118.

A via 140 extends through each word line and the second and third dielectric regions. The sidewalls of each via 140 are lined with a dielectric layer 122. A semi-conductive material 113 fills the vias 140. The semi-conductive material 113 is, for example, tin selenide, but other conductive materials can be used. A conductive capping layer 114 is over each via 140, semi-conductive material 113 and insulating liner 122.

FIGS. 2B and 2C are top down views of a portion of the array 100. As shown in FIGS. 2B and 2C, the digit lines 111 and word lines 112 are substantially perpendicular or orthogonal to one another. Each via 140 extends through a portion of a word line 112 to a digit line 111. As shown in FIG. 2B, the vias 140 can be surrounded by a word line 112. Alternatively, as illustrated in FIG. 2C, the vias 140 can be located at a lateral edge of a word line 112. When the vias 140 disrupt less of the word lines 112, as in FIG. 2C, the resistance of the word lines 112 is improved as compared to the embodiment of FIG. 2B.

Each access transistor 110 includes a digit line 111, word line 112, capping layer 114 and semi-conductive material 113. The digit line 111 and capping layer 114 serve as first and second source/drain regions of the access transistor 110, respectively. The semi-conductive material 113 forms the channel region of the access transistor 110.

The memory elements 135 also include one or more layers of resistance variable material, and may also include other materials layers. In the illustrated embodiment, the memory elements 135 include a stack 130 of layers 131, 132, 133. The stack 130 is formed over the capping layers 114 and third dielectric region 121.

In the exemplary embodiment shown in FIG. 2A, the memory cell stack 130 includes, for example, a chalcogenide material layer 131, a tin-chalcogenide layer 132, and an optional metal layer 133. The invention, however, is not limited to such embodiments, and the stack 130 can include additional or fewer layers of other materials suitable for forming a resistance variable memory element. For example, the stack 130 can include a second chalcogenide material layer (not shown) over the metal layer 133. The second chalcogenide layer may be a same material as the chalcogenide layer 131 or a different material.

In the illustrated embodiments, the chalcogenide material layer 131 is e.g., germanium selenide (GexSe100−x). The germanium selenide may be within a stoichiometric range of about Ge33Se67 to about Ge60Se40. The chalcogenide material layer 131 may be between about 100 Å and about 1000 Å thick, e.g., about 300 Å thick. Layer 131 need not be a single layer, but may also be comprised of multiple chalcogenide sub-layers having the same or different stoichiometries. The chalcogenide material layer 131 is in electrical contact with the capping layers 114.

Over the chalcogenide material layer 131 is an optional layer of metal-chalcogenide 132, such as tin-chalcogenide (e.g., tin selenide (Sn1+/−xSe, where x is between about 1 and about 0)), or silver-chalcogenide (e.g., silver selenide). It is also possible that other chalcogenide materials may be substituted for selenium, such as sulfur, oxygen, or tellurium. The layer 132 in the exemplary embodiment is a layer of tin-chalcogenide layer and may be about 100 Å to about 400 Å thick; however, its thickness depends, in part, on the thickness of the underlying chalcogenide material layer 131. The ratio of the thickness of the tin-chalcogenide layer 132 to that of the underlying chalcogenide material layer 131 may be between about 5:1 and about 1:3.

An optional metal layer 133 is provided over the tin-chalcogenide layer 132, with silver (Ag) being the exemplary metal. This metal layer 133 is between about 300 Å and about 500 Å thick.

Although in the illustrated exemplary embodiments of the invention, stack 130 is shown including layers 131, 132, 133, it should be appreciated that one or more of layers 131,132, 133 may be excluded and other layers may be included. Non limiting examples of materials and layers that can be included in stack 130 and materials for electrode 114 are discussed in various patents and patent applications assigned to Micron Technology, Inc., including, but not limited to the following: U.S. patent application Ser. No. 10/765,393; U.S. patent application Ser. No. 09/853,233; U.S. patent application Ser. No. 10/022,722; U.S. patent application Ser. No. 10/663,741; U.S. patent application Ser. No. 09/988,984; U.S. patent application Ser. No. 10/121,790; U.S. patent application Ser. No. 09/941,544; U.S. patent application Ser. No. 10/193,529; U.S. patent application Ser. No. 10/100,450; U.S. patent application Ser. No. 10/231,779; U.S. patent application Ser. No. 10/893,299; U.S. patent Ser. No. 10/077,872; U.S. patent application Ser. No. 10/865,903; U.S. patent application Ser. No. 10/230,327; U.S. patent application Ser. No. 09/943,190; U.S. patent application Ser. No. 10/622,482; U.S. patent application Ser. No. 10/081,594; U.S. patent application Ser. No. 10/819,315; U.S. patent application Ser. No. 11/062,436; U.S. patent application Ser. No. 10/899,010; and U.S. patent application Ser. No. 10/796,000, which are incorporated herein by reference.

A second electrode 150 is formed over the stack 130. The second electrode 150 is, for example tungsten, but other conductive materials can be used. Although the layers 131, 132, 133 of stack 130 and second electrode 150 are shown as blanket layers, they could instead be patterned as desired. For example, one or more layers of the stack 130 and/or the second electrode 150 can be patterned as described in copending U.S. patent application Ser. No. 11/111,836, assigned to Micron Technology, Inc., which is incorporated herein by reference.

The access transistor 110 enables a true cross point architecture for the array 100. Accordingly, the array 100 can have a 4F2 structure and provides a more efficient use of the substrate 101 surface area.

The formation the memory array 100 (FIGS. 2A-2C) according to an exemplary embodiment of the invention is now described in connection with FIGS. 3A-3J. No particular order is required for any of the actions described herein, except for those logically requiring the results of prior actions. Accordingly, while the actions below are described as being performed in a general order, the order is exemplary only and can be altered if desired. Although the formation of only a portion of an array 100 is described, it should be appreciated that the memory array 100 can include additional memory elements 135 and access transistors 110, which can be formed concurrently.

As shown by FIG. 3A, a substrate 101 is initially provided. As indicated above, the substrate 101 can be semiconductor-based or another material useful as a supporting structure. A first dielectric region 119 is formed over the substrate 101. The first dielectric region 119 can be one or more layers of dielectric material, such as silicon nitride, a low dielectric constant material, or other insulators known in the art. The first dielectric region 119 can be formed by any known method. A digit line 111 is formed over the first dielectric region 119. The digit line 111 can be formed by depositing and patterning a conductive material, such as tungsten or other conductive material.

Referring to FIG. 3B, a second dielectric region 120 is formed over the first dielectric region 119 and the digit line 111. The second dielectric region 120 can be one or more layers of dielectric material (such as silicon nitride, a low dielectric constant material, or other insulators known in the art) and can be formed by any known method.

As shown in FIG. 3C, a conductive layer 112 is formed over the second dielectric region 120. An optional insulating layer 118 is formed over the conductive material. If desired, the insulating layer 118 may be omitted. The conductive layer 112 and insulating layer 118 are patterned to form a word line 112 having an insulating layer 118. In the illustrated embodiment, the word line 112 is tungsten and the insulating layer 118 is a nitride, but other conductive and insulating materials can be used.

Referring to FIG. 3D, a third dielectric region 121 is formed over the word line 112 and insulating layer 118. The third dielectric region 121 can be one or more layers of dielectric material (such as silicon nitride, a low dielectric constant material, or other insulators known in the art) and can be formed by any known method. In the illustrated embodiment, the third dielectric region 121 includes an uppermost layer of nitride.

As depicted in FIG. 3E, a via 140 is formed through the third dielectric region 121, insulating layer 118, word line 112, and second dielectric region 120 to expose the surface of the digit line 111. The via 140 is formed at an intersection of the word line 112 and digit line 111. As shown in FIGS. 2B and 2C, the via 140 can be formed such that it is surrounded by word line 112 (FIG. 2B) or positioned at a lateral edge of the word line 112 (FIG. 2C).

An oxide layer 122 is formed over the third dielectric region 121 and within the via 140 as shown in FIG. 3F. The oxide layer 122 lines the sidewalls of the via 140. An etch step is performed to remove the oxide layer 122 from the bottom of the via 140 and the surface of the third dielectric region 140, as shown in FIG. 3G.

As illustrated in FIG. 3H, a semi-conductive material 113 is deposited over the third dielectric region 121 and fills the via 140. In the illustrated embodiment, the semi-conductive material 113 is tin selenide, but other conductive materials, for example, tin telluride, among others, can be used.

The tin selenide 113 outside the via 140 is removed, as shown in FIG. 3I. For this, a chemical mechanical polish (CMP) step is performed. As is known in the art, the CMP can be stopped upon reaching the upper nitride layer of the third dielectric region 121. Alternatively, a mask layer (not shown) can be formed having a negative image of the via 140. An etch process could then be used to remove the tin selenide 113 unprotected by the mask. As a further alternative, a blanket dry etch step can be performed, leaving the via 140 at least partially filled with tin selenide 113.

As shown in FIG. 3J, the formation of the access transistor is completed by forming a conductive cap 114 over the via 140 and in contact with the tin selenide 113. For this, a conductive layer is formed over the third dielectric region 121 and via 140. The conductive layer is patterned to form approximately a negative image of the via 140. In the illustrated embodiment, the conductive cap 114 is tungsten, but other conductive materials can be used.

Memory elements 135 can be formed in contact with the conductive cap 114. For example, at least one layer of a memory stack 130 is formed over the second insulating region 121 and capping layer 114 to achieve the structure shown in FIG. 2A.

In the illustrated embodiment, a chalcogenide material layer 131 is formed over the capping layer 114 and third insulating region 121. Formation of the chalcogenide material layer 131 may be accomplished by any suitable method, for example, by sputtering. Additional layers of the memory stack 130 are formed over the layer 131. In the illustrated embodiment, an optional metal-chalcogenide layer 132 (e.g., tin-chalcogenide) is formed over and in contact with the chalcogenide material layer 131. The metal-chalcogenide layer 132 can be formed by any suitable method, e.g., physical vapor deposition, chemical vapor deposition, co-evaporation, sputtering, among other techniques. An optional metal layer 133 is formed over the tin-chalcogenide layer 132. The metal layer 133 is preferably silver (Ag), or at contains silver, and is formed to a preferred thickness of about 300 Å to about 500 Å. The metal layer 133 may be deposited by any technique known in the art. Also, a second electrode layer 150 is deposited over the stack 130. Although the layers 131, 132, 133 of the stack 130 and the second electrode layer 150 are shown as blanket layers, one or more of these layers can be patterned as desired.

FIG. 4 illustrates a processor system 400 which includes a memory circuit 448, e.g., a memory device, which employs memory array 100 constructed according to the invention. The processor system 400, which can be, for example, a computer system, generally comprises a central processing unit (CPU) 444, such as a microprocessor, a digital signal processor, or other programmable digital logic devices, which communicates with an input/output (I/O) device 446 over a bus 452. The memory circuit 448 communicates with the CPU 444 over bus 452 typically through a memory controller.

In the case of a computer system, the processor system 400 may include peripheral devices such as a floppy disk drive 454 and a compact disc (CD) ROM drive 456, which also communicate with CPU 444 over the bus 452. Memory circuit 448 is preferably constructed as an integrated circuit, which includes a memory array 100 according to the invention. If desired, the memory circuit 448 may be combined with the processor, for example CPU 444, in a single integrated circuit.

The above description and drawings are only to be considered illustrative of exemplary embodiments, which achieve the features and advantages of the present invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.

Claims

1. A memory array comprising:

a substrate;
a plurality of access transistors over the substrate, each access transistor comprising a channel region between first and second electrodes, the channel region, first electrode and second electrode being vertically stacked over the substrate, the channel region being in contact with a top surface of the first electrode and completely isolated from the substrate by the first electrode; and
a resistance variable material and a first portion of metal-chalcogenide material over and electrically coupled to a plurality of second electrodes of respective access transistors and forming a plurality of resistance variable memory elements, each accessed by the respective access transistor, wherein the channel region comprises a second portion of the metal-chalcogenide material.

2. The array of claim 1, wherein the access transistor further comprises a gate, and wherein the gate is a conductive line.

3. The array of claim 2, wherein the channel region comprises a semi-conductive material extending through the conductive line and being in contact with the first electrode.

4. The array of claim 3, wherein the second electrode is an electrode for the at least one memory element.

5. The array of claim 3, wherein the semi-conductive material is laterally surrounded by the conductive line.

6. The array of claim 3, wherein the semi-conductive material is only partially laterally surrounded by the conductive line.

7. The array of claim 1, wherein the channel region comprises a semi-conductive material within a via.

8. The array of claim 7, wherein sidewalls of the via are lined with an insulating layer.

9. The memory array of claim 1, wherein the resistance variable material is in contact with at least a portion of the second electrode of each respective access transistor.

10. A processor system, the system comprising:

a processor; and
a memory device coupled to the processor, the memory device comprising a memory array, the memory array comprising:
a plurality of transistors, each transistor comprising a channel region between first and second source/drain regions, the channel region, first source/drain region and second source/drain region being vertically stacked over the substrate, the first source/drain region being a first conductive line, the conductive line being completely isolated from a substrate by a dielectric region, the channel region being in contact with a top surface of the first conductive line, and
a plurality of blanket layers stacked over and electrically coupled to a plurality of second source/drain regions of respective transistors and forming a plurality of memory elements,
each accessed by the respective transistor, the plurality of layers comprising a resistance variable material and a metal-chalcogenide material, wherein the channel region comprises the metal-chalcogenide material.

11. The system of claim 10, wherein the access transistor further comprises a gate and the gate is a second conductive line.

12. The system of claim 11, and wherein the channel region comprises a semi-conductive material extending through the second conductive line and is in contact with the first conductive line, and wherein the second source/drain region is a conductive layer in contact with the channel region.

13. The system of claim 12, wherein the conductive layer is the first electrode.

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Patent History
Patent number: 7579615
Type: Grant
Filed: Aug 9, 2005
Date of Patent: Aug 25, 2009
Patent Publication Number: 20070034921
Assignee: Micron Technology, Inc. (Boise, ID)
Inventors: Jon Daley (Boise, ID), Kristy A. Campbell (Boise, ID), Joseph F. Brooks (Boise, ID)
Primary Examiner: Anh Phung
Assistant Examiner: Michael Lulis
Attorney: Dickstein Shapiro LLP
Application Number: 11/199,251
Classifications
Current U.S. Class: In Array (257/5); Bistable Switching Devices, E.g., Ovshinsky-effect Devices (epo) (257/E45.002); Amorphous (electrical) (365/163)
International Classification: H01L 45/00 (20060101);