Patents by Inventor Joseph Fjelstad

Joseph Fjelstad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020179325
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.
    Type: Application
    Filed: July 23, 2002
    Publication date: December 5, 2002
    Applicant: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad
  • Patent number: 6486547
    Abstract: A sheet such as a polymeric dielectric has elongated lead regions partially separated from the main region of the sheet by gaps in the sheet, and has conductors extending along the lead regions. The lead regions are connected to contacts on a microelectronic element, and the microelectronic element is moved away from the main region of the sheet, thereby bending the lead regions downwardly to form leads projecting from the main region of the sheet.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: November 26, 2002
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6486003
    Abstract: A method of fabricating a microelectronic package comprising an expandable structure includes the steps of providing first and second microelectronic elements having electrically conductive parts, providing the expandable structure between the microelectronic elements, connecting the electrically conductive parts together so that the microelectronic elements are electrically interconnected, and expanding the expandable structure after the connecting step so that the microelectronic elements move away from one another. The expandable structure is more rigid before the expanding step and less rigid after the expanding step. During the expanding step, the expandable structure remains in contact with the microelectronic elements and the microelectronic elements remain electrically interconnected. A microelectronic package including an expandable structure is also disclosed.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: November 26, 2002
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20020168797
    Abstract: A semiconductor chip packaging assembly comprising a frame having a central aperture, a flexible substrate attached to the frame across the central aperture, and a unitary support structure having a plurality of apertures therethrough attached to the substrate within the central aperture of the frame with at least some of the substrate terminals underlying the unitary support structure. A chip is disposed within each aperture and attached to the substrate with the electrical contacts of the chip connected to the substrate terminals. A compliant layer is disposed between the substrate and the unitary support structure and between the substrate and the chip.
    Type: Application
    Filed: March 12, 2002
    Publication date: November 14, 2002
    Inventors: Thomas H. DiStefano, Joseph Fjelstad
  • Patent number: 6468836
    Abstract: A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: October 22, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Joseph Fjelstad, John W. Smith
  • Patent number: 6465878
    Abstract: A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: October 15, 2002
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Patent number: 6465747
    Abstract: A microelectronic assembly includes a component having one or more conductive pads, with each conductive pad having a plurality of solder-wettable strips extending outwardly away from a center, the solder wettable strips being bounded by non solder-wettable material. The microelectronic assembly also includes a composite conductive element positioned atop at least one of the conductive pads, the composite conductive element including a solid conductive core and a layer of solder material overlying the solid conductive core, the solid conductive core having a higher melting temperature than the layer of solder material.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: October 15, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad
  • Patent number: 6458681
    Abstract: A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: October 1, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad
  • Publication number: 20020115236
    Abstract: A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or “assembly”, contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools once the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process.
    Type: Application
    Filed: February 9, 1998
    Publication date: August 22, 2002
    Inventors: JOSEPH FJELSTAD, KONSTANTINE KARAVAKIS
  • Publication number: 20020103445
    Abstract: The present invention relates, generally, to thermography catheters and, more particularly, to thermography catheters which use flex circuit technology to create the connections and thermocouples used to detect hot spots (areas with high metabolic activity) of the atherosclerotic plaque, vascular lesions, and aneurysms in human vessels.
    Type: Application
    Filed: August 24, 2001
    Publication date: August 1, 2002
    Inventors: David A. Rahdert, Michael Perry, Brett A. Herscher, Joseph Fjelstad, Thomas H. Campbell
  • Publication number: 20020100961
    Abstract: A microelectronic assembly includes a microelectronic element having a first surface with a plurality of contacts accessible at the first surface, and a compliant layer over the first surface of the microelectronic element, the compliant layer including a plurality of bumped protrusions and openings adjacent the bumped protrusions for providing access to the contacts, wherein each bumped protrusion includes a top surface and at least one sloping edge. The microelectronic assembly also includes conductive terminals over the top surfaces of the bumped protrusions, and a plurality of conductive bond ribbons having first ends in engagement with the contacts, second ends in engagement with the terminals and intermediate sections extending along the sloping edges for electrically interconnecting the contacts and the terminals.
    Type: Application
    Filed: March 26, 2002
    Publication date: August 1, 2002
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Publication number: 20020094671
    Abstract: A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.
    Type: Application
    Filed: March 13, 2002
    Publication date: July 18, 2002
    Inventors: Thomas H. Distefano, Joseph Fjelstad
  • Patent number: 6417029
    Abstract: A method of making a semiconductor chip assembly includes the steps of providing a semiconductor chip with contacts and a dielectric substrate wiring layer with terminals, forming a plurality of conductive elastomeric posts such that each post connects one terminal to one contact, and injecting a compliant material between the semiconductor chip and the dielectric substrate wiring layer to form a compliant layer.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: July 9, 2002
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20020081781
    Abstract: A connection component for use in making microelectronic element assemblies which has peelable leads that are formed on a dielectric support structure. One end of each lead is permanently connected to the support structure and the opposite end of the lead is releasably connected to the support structure. When the releasable end of the lead is bonded to a contact on a semiconductor chip, the releasable end of the lead can be peeled from the support structure such that the chip may be moved away from the support structure. A compliant layer may be disposed between the chip and the support structure. If a compliant material is injected between the chip and the support structure to form the compliant layer, the compliant material will lift the chip away from the support structure and facilitate the peeling of the leads from the support structure.
    Type: Application
    Filed: December 28, 2001
    Publication date: June 27, 2002
    Inventors: Thomas H. DiStefano, Joseph Fjelstad, Belgacem Haba, Owais Jamil, Konstantine Karavakis, David Light, John W. Smith
  • Publication number: 20020081777
    Abstract: A method of manufacturing a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of terminals exposed at the first surface, providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface, forming a plurality of conductive elastomeric posts which connect each of the contacts to one of the terminals, and injecting a compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element to form a compliant layer.
    Type: Application
    Filed: February 20, 2002
    Publication date: June 27, 2002
    Inventor: Joseph Fjelstad
  • Publication number: 20020075016
    Abstract: A probe card for testing an electrical element such as a semiconductor wafer or a printed wiring board includes a substrate with circuitry thereon, an encapsulant layer overlying the substrate and a multiplicity of leads extending upwardly from the substrate through the encapsulant layer to terminals, the terminals projecting above the encapsulant layer. The probe card can be engaged with the electronic element so that the tips of the leads bear on the contact pads of the electronic element, and so that the leads and encapsulant layer deform to accommodate irregularities in the electronic element or probe card. The card can be made by providing the substrate, a sacrificial layer and leads extending between the sacrificial layer and substrate, moving the substrate and sacrificial layer away from one another to deform the leads and injecting a curable material around the leads to form the encapsulant layer.
    Type: Application
    Filed: October 24, 2001
    Publication date: June 20, 2002
    Inventor: Joseph Fjelstad
  • Publication number: 20020068426
    Abstract: A method of making a microelectronic assembly includes juxtaposing a first element, such as a dielectric sheet having conductive leads thereon with a second element, such as a semiconductor chip, having contact thereon, and wire bonding the conductive leads on the first element to the contacts on the second element so that elongated bonding wires extend between the conductive leads and the contacts. After the wire bonding step, the first and second elements are moved through a pre-selected displacement relative to one another so as to deform the bonding wires. A flowable dielectric material may be introduced between the first and second elements and around the bonding wires during or after the moving step. The flowable material may be cured to form an encapsulant around at least a portion of the bonding wires.
    Type: Application
    Filed: January 22, 2001
    Publication date: June 6, 2002
    Inventors: Joseph Fjelstad, Masud Beroz, John W. Smith, Belgacem Haba
  • Patent number: 6373128
    Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: April 16, 2002
    Assignee: Tessera, Inc.
    Inventors: Konstantine Karavakis, Joseph Fjelstad
  • Patent number: 6361959
    Abstract: Electrically conductive elements such as terminals and leads are held on a support structure by a degradable connecting layer such as a adhesive degradable by heat or radiant energy. After connecting these elements to a microelectronic element such as a chip or wafer, the conductive elements are released from the support structure by degrading the connecting layer. The support structure desirably has a predictable, isotropic coefficient of thermal expansion and such coefficient of thermal expansion may be close to that of silicon to minimize the effect of the temperature changes. The conductive elements may be mounted on a plurality of individual tiles rather than on an unitary sheet covering an entire wafer to minimize dimensional changes when the dielectric is released from the support structure.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: March 26, 2002
    Assignee: Tessera, Inc.
    Inventors: Masud Beroz, Joseph Fjelstad, Belgacem Haba, Christopher M. Pickett, John Smith
  • Patent number: 6357112
    Abstract: A connection component for use in making microelectronic element assemblies, has peelable leads that are formed on a dielectric support structure. One end of each lead is permanently connected to the support structure and the opposite end of the lead is releasably connected to the support structure. When the releasable end of the lead is bonded to a contact on a semiconductor chip, the releasable end of the lead can be peeled from the support structure such that the chip may be moved away from the support structure. A compliant layer may be disposed between the chip and the support structure. If a compliant material is injected between the chip and the support structure to form the compliant layer, the compliant material will lift the chip away from the support structure and facilitate the peeling of the leads from the support structure.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: March 19, 2002
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad, Belgacem Haba, Owais Jamil, Konstantine Karavakis, David Light, John W. Smith