Patents by Inventor Joseph Fjelstad

Joseph Fjelstad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6265759
    Abstract: A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: July 24, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad, John W. Smith
  • Patent number: 6261863
    Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions. A method of making a connection component includes removing material from the conductive structures or the support layer or both to form the anchors.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: July 17, 2001
    Assignee: Tessera, Inc.
    Inventors: Masud Beroz, Thomas H. DiStefano, Anthony B. Faraci, Joseph Fjelstad, Belgacem Haba
  • Publication number: 20010007375
    Abstract: A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.
    Type: Application
    Filed: February 6, 2001
    Publication date: July 12, 2001
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Publication number: 20010006253
    Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions.
    Type: Application
    Filed: February 6, 2001
    Publication date: July 5, 2001
    Inventors: Masud Beroz, Thomas H. DiStefano, Anthony B. Faraci, Joseph Fjelstad, Belgacem Haba
  • Patent number: 6253992
    Abstract: Bonding material balls such as solder balls are applied onto contacts of a semiconductor chip or other microelectronic unit using an escapement mechanism which feeds one solder ball per cycle into each aperture of a stencil. The apparatus reliably places one solder ball on each contact of the microelectronic unit.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: July 3, 2001
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20010005044
    Abstract: A microelectronic assembly includes a microelectronic element having a front face including contacts, a back surface remote from the front face and edges extending therebetween. A mass of a dielectric material at least partially encapsulates the microelectronic element. The microelectronic assembly includes conductive units embedded in the mass of dielectric material at at least one edge of the microelectronic element, whereby at least some of the conductive units are exposed on oppositely-facing exterior surfaces of the mass of dielectric material. Conductive elements extend through the mass of dielectric material and electrically interconnect the contacts with the conductive units.
    Type: Application
    Filed: February 16, 2001
    Publication date: June 28, 2001
    Inventor: Joseph Fjelstad
  • Patent number: 6247228
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: June 19, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Joseph Fjelstad
  • Patent number: 6239384
    Abstract: A microelectronic connection component has flexible leads formed by polymeric strips with metallic conductors thereon. The metallic conductors may be very thin, desirably less than 5 microns thick, and provide good fatigue resistance. Each strip may have two conductors thereon, one serving as a principal or first signal conductor for connection to a first contact on a chip or other microelectronic element and the other serving as potential reference or ground conductor, or as a second signal conductor connected to a second contact on the chip. The system provides enhanced resistance to crosstalk and rapid signal transmission, and is compatible with differential signal transmission.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: May 29, 2001
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6239386
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts expand radially and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by conductive bonding material carried on the contacts themselves.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: May 29, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine N. Karavakis, Zlata Kovac, Joseph Fjelstad
  • Patent number: 6228686
    Abstract: A sheet such as a polymeric dielectric has elongated lead regions partially separated from the main region of the sheet by gaps in the sheet, and has conductors extending along the lead regions. The lead regions are connected to contacts on a microelectronic element, and the microelectronic element is moved away from the main region of the sheet, thereby bending the lead regions downwardly to form leads projecting from the main region of the sheet.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: May 8, 2001
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6229100
    Abstract: A connector for microelectronic elements includes electrically conductive, elongated leads having contact portions underlying a compliant layer. The contact portion of each lead overlies a pedestal portion of the compliant layer. The pedestal portion is at least partially isolated from the remaining portion of the compliant layer by gaps in the compliant layer. The pedestals may thus deflect horizontally, compensating for relative movement between the connector and the microelectronic element. Portions of the leads spanning the gaps may be curved to facilitate deflection. The pedestals may be attached to a substrate having terminals. A terminal end of each lead is then electrically connected to the terminal in the substrate, either through a plated through-hole, or by bending downward and bonding. The pedestals may support a plurality of leads along their length.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: May 8, 2001
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6221750
    Abstract: An element such as a semiconductor wafer or other body is provided with leads by applying a sacrificial layer over the front surface of the body depositing leads onto the sacrificial layer so that the leads are connected to contact pads on the body and removing the sacrificial layer from beneath the leads. The sacrificial layer may incorporate thin and thick regions so that portions of the leads projecting upwardly away from the body will be formed on the thick regions of the sacrificial layer.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: April 24, 2001
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6218213
    Abstract: Flexible leads for making electrical connection in microelectronic components include a frangible intermediate section. The frangible intermediate section is formed by a region within the lead having weakened mechanical integrity. The frangible intermediate section is made by providing a sacrificial metal layer and forming a projection on the surface of the metal layer from a portion thereof. Lead forming material is deposited onto the surface of the sacrificial metal layer and over the projection. A dielectric layer is formed on the surface of the lead forming material. Upon removing the sacrificial metal layer, a frangible intermediate section is formed within the lead forming material at the location of the projection.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: April 17, 2001
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, John W. Smith
  • Patent number: 6211690
    Abstract: A testing fixture for microelectronic elements is in the nature of an interposer which is operative for receiving a plurality of test probes. The interposer enables the simultaneous testing of contacts on the microelectronic element which are arranged in both high contact pitch density areas and normal contact pitch density areas. The contacts on the microelectronic element within the high contact pitch density areas are accessed by conductive leads on the interposer having rigid portions arranged in a corresponding high contact pitch density.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: April 3, 2001
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6211572
    Abstract: A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or “assembly”, contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools since the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: April 3, 2001
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Patent number: 6205660
    Abstract: Microelectronic contacts, such as flexible, tab-like, cantilever contacts, are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: March 27, 2001
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, John W. Smith, Thomas H. Distefano, James Zaccardi, A. Christian Walton
  • Patent number: 6208025
    Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: March 27, 2001
    Assignee: Tessera, Inc.
    Inventors: Pieter H. Bellaar, Thomas H. Distefano, Joseph Fjelstad, Christopher M. Pickett, John W. Smith
  • Patent number: 6204091
    Abstract: A method of encapsulating a microelectronic assembly includes providing one or more microelectronic assemblies having one or more elements defining exterior surfaces and an array of terminals exposed at the exterior surfaces, the one or more elements defining one or more apertures through the exterior surfaces. A layer of a curable barrier material is then provided on a supporting element. The barrier layer has openings therein in a pattern corresponding to the array of terminals on the one or more microelectronic assemblies. The supporting element and the one or more microelectronic elements are then assembled together so that the layer of barrier material contacts the exterior surfaces and covers the apertures and so that the openings in the layer of barrier material are aligned with the terminals. The barrier material is then cured while in contact with the exterior surfaces to thereby form a barrier layer covering the apertures.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6196042
    Abstract: A tool having a coining projection is operative for forming a frangible portion in a lead of a microelectronic connection component by application of a compressive force. The coining projection is supported on a pedestal formed from a tool body. In an alternative embodiment, the pedestal is formed on a backing plate for use in circuits up construction. The pedestal is sized and shaped so as to be received within a gap formed in a support layer for the leads. By application of the compressive force, the coining projection will penetrate the lead within the region of the gap to form the frangible portion.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: March 6, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Joseph Fjelstad, Belgacem Haba
  • Patent number: 6157075
    Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: December 5, 2000
    Assignee: Tessera, Inc.
    Inventors: Konstantine Karavakis, Joseph Fjelstad