Abstract: A component for mounting semiconductor chips or other microelectronic units includes a compliant, sheet-like body with arrays of sheet-like conductive pads on upper and lower surfaces of the body. Flexible leads extending through the body interconnect conductive pads on the upper and lower surfaces. The leads are desirably formed from wire, such as gold wire, that is bonded to the conductive pads using a conductive epoxy or a eutectic bonding alloy. The component is made using sacrificial base sheets having conductive terminal portions to which the leads are initially bonded. The compliant body is formed by injecting a flowable material between the base sheets, curing the material and removing the base sheets by etching. The flowable material surrounds the leads such that the leads are supported by the cured compliant layer. The component may be used as an interposer or as a test socket.

Abstract: A method of encapsulating a microelectronic assembly includes providing one or more microelectronic assemblies having one or more elements defining exterior surfaces and an array of terminals exposed at the exterior surfaces, the one or more elements defining one or more apertures through the exterior surfaces. A layer of a curable barrier material is then provided on a supporting element. The barrier layer has openings therein in a pattern corresponding to the array of terminals on the one or more microelectronic assemblies. The supporting element and the one or more microelectronic elements are then assembled together so that the layer of barrier material contacts the exterior surfaces and covers the apertures and so that the openings in the layer of barrier material are aligned with the terminals. The barrier material is then cured while in contact with the exterior surfaces to thereby form a barrier layer covering the apertures.

Abstract: A method for the removal of voids and gas bubbles within uncured or partially cured microelectronic component enapsulants and adhesive/chip attach layers. A sealed void or gas bubble within a gap between a microelectronic component and a supporting substrate is substantially eliminated through the application of a uniform pressure (isostatic or hydrostatic) and energy such that a substantially void/bubble free interposer is created.

Abstract: A semiconductor chip assembly with a frame having an aperture, a continuous rail enclosing the aperture and bonds pads disposed on the top surface of the continuous rail; a semiconductor chip having contacts on its top surface fitted within the aperture; a plurality of wire loops connecting the bond pads to the contacts, and a compliant layer disposed over the first surface of the semiconductor chip and the plurality of wire loops such that the top portion of each wire loop is exposed. The semiconductor chip assembly can be incorporated into a larger assembly by connecting the wire loops to connection pads on an external substrate.

Abstract: A method of manufacturing a semiconductor chip package. A sacrificial layer is used as a base to selectively form an array of conductive pads such that a central region is defined by the pads. A back surface of a semiconductor chip is next attached to the sacrificial layer within the central region between the pads so that the contact bearing surface of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to respective pads, typically by wire bonding a wire therebetween. A curable, dielectric liquid encapsulant is then deposited on the sacrificial layer such that the pads, electrical connections and chip are fully encapsulated, as by an overmolding operation. The encapsulant is then cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.

Abstract: A connector for microelectronic elements includes a sheetlike body having a plurality of active contacts arranged in a regular grid pattern. The active contacts may include several sheetlike metallic projections extending inwardly around a hole in the sheetlike element, on a first major surface of the sheetlike element. A support structure such as a grid array of noncollapsing structural posts is on a second major surface of the sheetlike element, and each of the posts is electrically connected to one of the active contacts. The grid array of posts and the grid array of active contacts are offset from one another so that an active contact is surrounded by several posts. The posts support the sheetlike element spaced away from a substrate to which the posts are attached. A microelectronic element having bump leads thereon may be engaged by contacting the bump leads with the active contacts, and deflecting the sheetlike element between the bump leads on one side and the posts on the other side.

Abstract: Flexible connectors having substantially vertical conductive legs allowing the connectors to accommodate deflection in the lateral directions (x-y directions in the plane of the connectors) induced by CTE mismatches between a chip and a substrate during thermal cycling of the chip. The connectors also accommodate deflections in the vertical direction (z direction--perpendicular to the plane of the connectors) which may be caused by connection to a substrate. Such substantially vertical leg features are formed using projection lithography, such as projected x-ray or ultra-violet ("UV") radiation, to selectively expose a photoresist layer such that the substantially vertical metal features may be formed by plating or etching. The sacrificial layer may be in the form of an array of posts, such that "stool-like" post connectors are created, or may be in the form of an array of apertures, such that "basket-like" receptacles or sockets are created.

Abstract: A method of manufacturing a semiconductor chip package. A sacrificial layer is used as a base to selectively form an array of conductive pads such that a central region is defined by the pads. A back surface of a semiconductor chip is next attached to the sacrificial layer within the central region between the pads so that the contact bearing surface of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to respective pads, typically by wire bonding a wire therebetween. A curable, dielectric liquid encapsulant is then deposited on the sacrificial layer such that the pads, electrical connections and chip are fully encapsulated, as by an overmolding operation. The encapsulant is then cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.

Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.

Abstract: A structure including a conductive, preferably metallic conductive layer is provided with leads on a bottom surface. The leads have fixed ends permanently attached to the structure and free ends detachable from the structure. The structure is engaged with a microelectronic element such as a semiconductor chip or wafer, the free ends of the leads are bonded to the microelectronic element, and the leads are bent by moving the structure relative to the microelectronic element. Portions of the conductive layer are removed, leaving residual portions of the conductive layer as separate electrical terminals connected to at least some of the leads. The conductive layer mechanically stabilizes the structure before bonding, and facilitates precise registration of the leads with the microelectronic element. After the conductive layer is converted to separate terminals, it does not impair free movement of the terminals relative to the microelectronic element.

Abstract: A method of making a assembly including the steps of fitting a chip within an aperture in a frame, connecting the bond pads on the frame to the contacts on the chip by forming wire loops therebetween, dispensing a compliant material over the frame, chip and wire loops for form a compliant layer, and plasma etching the top surface of the compliant layer to expose the top portion of each wire loop. The semiconductor chip assembly can then be incorporated into a larger assembly by connecting the wire loops to connection pads on an external substrate.

Abstract: A connector for microelectronic elements includes electrically conductive, elongated leads having contact portions underlying a compliant layer. The contact portion of each lead overlies a pedestal portion of the compliant layer. The pedestal portion is at least partially isolated from the remaining portion of the compliant layer by gaps in the compliant layer. The pedestals may thus deflect horizontally, compensating for relative movement between the connector and the microelectronic element. Portions of the leads spanning the gaps may be curved to facilitate deflection. The pedestals may be attached to a substrate having terminals. A terminal end of each lead is then electrically connected to the terminal in the substrate, either through a plated through-hole, or by bending downward and bonding. The pedestals may support a plurality of leads along their length.

Abstract: A method of making a solder connection. An element bearing a solder mass is forcibly engaged with another element bearing a resilient metallic contact so that the contact wipes the surface of the solder mass and so that the contact is deformed and bears against the wiped surface. While the contact is in its deformed condition, the contact and solder mass are brought to an elevated bonding temperature sufficient to soften the solder, so that the contact penetrates into the solder mass under the influence of its own resilience. The contact bonds with the pure solder inside the solder mass, so that the effective bonding can be achieved even without flux.

Abstract: A method of forming a microelectronic assembly having an element with contacts on a front surface thereof, an interposer with a plurality of connecting terminals in a connecting terminal region and bonding terminals in a bonding terminal region electrically connected to the connecting terminals includes the steps of juxtaposing the interposer with the microelectronic element so that the connecting terminals and bonding terminals of the interposer face away from the front surface of the element and so that the bonding terminal region is adjacent to the contacts of the microelectronic element; and connecting at least some of the contacts with at least some of the bonding terminals by a plurality of flexible leads while supporting the bonding terminals against the vertical movement to facilitate the connection.

Abstract: Microelectronic contacts, such as flexible, tab-like, cantilever contacts, are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a dielectric layer and leads extending across a surface of the dielectric layer. Each lead has one end permanently fastened to the dielectric layer and another end releasably bonded to the dielectric layer. The releasable end is held in place by a bond having a relatively low peel strength, desirably less than about 0.35.times.10.sup.6 dynes/cm.

Abstract: A method for the removal of voids and gas bubbles within uncured or partially cured microelectronic component encapsulants and adhesive/chip attach layers. A sealed void or gas bubble within a gap between a microelectronic component and a supporting substrate is substantially eliminated through the application of a uniform pressure (isostatic or hydrostatic) and energy such that a substantially void/bubble free interposer layer is created.

Abstract: A semiconductor chip package includes a substrate having a first surface and a second surface and a gap extending from the first surface to the second surface. The substrate defines a plane which is substantially parallel to the first and second surfaces. The substrate has conductive terminals accessible and the second surface and bond pads. Conductive leads extend across the gap whereby each lead electrically interconnects one of the conductive terminals and one of the bond pads. Each lead includes an expansion section within the gap which is laterally curved with respect to the plane. A semiconductor chip having a back surface and a face surface is assembled to the substrate. The face surface includes a plurality of contacts on the periphery of the face surface of the chip whereby the chip contracts are electrically connected to the bond pads on the substrate.

Abstract: A semiconductor chip connection component having numerous leads extending side-by-side across a gap in a support structure, each lead having a frangible section to permit detachment of one end of the lead from the support structure in a bonding process. The frangible sections are formed by treating the lead-forming material in an elongated treatment zone extending across the regions occupied by numerous leads. The process avoids the need for especially fine etching to form notches in the lateral edges of the leads.

Abstract: A connector for microelectronic includes a sheet-like body having a plurality of holes, desirably arranged in a regular grid pattern. Each hole is provided with a resilient laminar contact such as a ring of a sheet metal having a plurality of projections extending inwardly over the hole of a first major surface of the body. Terminals on a second surface of the connector body are electrically connected to the contacts. The connector can be attached to a substrate such a multi-layer circuit panel so that the terminals on the connector are electrically connected to the leads within the substrate. Microelectronic elements having bump leads thereon may be engaged with the connector and hence connected to the substrate, by advancing the bump leads into the holes of the connector to engage the bump leads with the contacts. The assembly can be tested, and if found acceptable, the bump leads can be permanently bonded to the contacts.