Abstract: A flash drive includes a housing comprising a front wall, a rear wall and an inner space formed by the front wall and the rear wall; a storage module disposed in the inner space; a plug head mounted at one end of the storage module; a positioning element positioning the storage module in the inner space of the housing in such a manner that the plug head protrudes from one end of the housing; and a cover pivoted to the front wall and the rear wall through an eccentric-rotation structure to cover or uncover the plug head.

Abstract: A flash drive includes a housing, a storage module, a plug head, a positioning element and a rotatable cover. The housing has an inner space formed by a front wall and a rear wall for accommodating other elements. The storage module has a metal sheet at one end for connecting a connecting plate including a plurality of metal terminals and a plurality of welding pads at the other end for connecting a plug head. The positioning element positions the storage module in the housing and the plug head protruding from a lateral wall of the housing (the top wall of the housing). The rotatable cover is eccentric-rotatablly disposed on the housing to cover or uncover the plug head.

Abstract: In an embodiment of the present invention, a GraphSLAM-like algorithm for signal strength SLAM is presented. This algorithm as an embodiment of the present invention shares many of the benefits of Gaussian processes yet is viable for a broader range of environments since it makes no signature uniqueness assumptions. It is also more tractable to larger map sizes, requiring O(N2) operations per iteration. In the present disclosure, an algorithm according to an embodiment of the present invention is compared to a laser-SLAM ground truth, showing that it produces excellent results in practice.

Abstract: A USB memory stick includes housing having a frame hole, a tray providing a fastening structure, and a memory attached to the tray and mounted with the tray in the housing. The memory includes a mating fastening structure fastened to the fastening structure of the tray, a stepped bottom wall formed of a plurality of steps rising one behind another, a plurality of vertical clearance compensation spring leaves respectively disposed corresponding to the steps, and a mating locating block forced into engagement with the frame hole of the housing.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Systems and methods are disclosed for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory. In an exemplary embodiment, the system includes a gating circuit, a sampling circuit, and a delay chain tracking circuit. The gating circuit receives a DQS enable signal and a input DQS signal, calibrates the DQS enable signal based on an amount of delay, and outputs the calibrated DQS signal. The sampling circuit provides the amount of delay to the gating circuit based on a sampling clock. The delay chain tracking circuit maintains the timing of the calibrated DQS enable signal over a plurality of clock cycles based on the sampling clock and a leveling clock.

Abstract: An integrated circuit may include a memory controller that interfaces with memory via one or more ports. A given port may be coupled to a comparator that receives data signals from the memory and a reference voltage signal and produces a corresponding output signal that identifies whether the data signals are logic one signals or logic zero signals. The memory controller may include detection circuitry coupled to the port that produces a target reference voltage signal for calibration of the reference voltage signal. The memory controller may include circuitry that produces the reference voltage signal based on control signals received from control circuitry. The control circuitry may generate the control signals to calibrate the reference voltage signal based on the target reference voltage.

Abstract: An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.

Abstract: A memory stick includes a casing having a connection member at a top end thereof for connection to a personal item and an opening at a bottom end thereof, a positioning tray insertable through the opening of the casing for positioning in the casing and having an angled upper bending plate extended from a top end thereof and defining with a bottom wall thereof a clamping space and an elastically deformable recessed portion defined in the angled upper bending plate, and a flash memory detachably inserted into the clamping space of the positioning tray and held down in place by the recessed portion.

Abstract: A circuit-includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements, each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.

Abstract: Embodiments provide a user interface for computing devices equipped with a touchscreen user interface/display and a digital camera that enhances a portion of a displayed image within a user's gaze. A user may calibrate their mobile device by touching a portion of the touchscreen with one or more fingers and following a moving image on the display with their eyes. The mobile device may track where a user is looking, and if the user is looking at the mobile device display, a portion of the display in the vicinity of the user's gaze may be enhanced in size. In an embodiment, if the user is looking at a virtual keyboard, key icons near the user's gaze may be increased in size commensurate with the user's finger tip size. In this manner, a user can accurately select individual keys in a virtual keyboard that fits within a mobile device display.

Abstract: Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input Output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: In a particular embodiment, a method includes applying a first feature detector to a portion of an image to detect a first set of features. The first set of features is used to locate a region of interest, and a boundary corresponding to the region of interest is determined. The method also includes displaying the boundary at a display. In response to receiving user input to accept the displayed boundary, a second feature detector is applied to an area of the image encapsulated by the boundary.

Abstract: A side-push retractable USB memory stick includes a PC board providing a data storage function, an insulative PC board holder accommodating the PC board and having a springy plate located on one lateral side thereof and a press portion outwardly protruded from the springy plate, a housing surrounding the insulative PC board holder and having a sliding slot located on one lateral side thereof for receiving the press portion and enabling the press portion to be operated by an external force to move a metal shield and a USB interface circuit of the PC board in and out of a front opening of the housing. A rear end block closed on a rear open side of the housing, and a front end block press-fitted into the front opening and defining a through hole for passing the metal shield and the USB interface circuit in and out of the housing.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: A USB memory stick includes comprises a casing comprising opposing top and bottom sides and a bottom opening in said bottom side, a PC board comprising a USB interface circuit and a memory chip package, a tray holding the PC board in the casing, a safety hook for fastening to a belt or strip-like object, and a hinge coupled between the casing and the safety hook for allowing a limited angle of rotation between the casing and the safety hook.

Abstract: In one exemplary embodiment, a system includes a social media tag-cloud generator. The social media tag-cloud generator obtains a user's social media feed and generates a topic tag cloud. The topic tag cloud includes a weighted key term representing a topic that occurs in the user's social media feed. A media-content source module obtains a first metadata about a first media-content episode. The media-content source module obtains a second metadata about a second media-content episode. The first metadata includes information to identify the first media content episode and to locate the first media content episode in a computer network. The second metadata includes information to identify the second media content episode and to locate the second media content episode in the computer network. A media-content scoring module determines a first score for the first media-content episode. The first score includes a first value judgment based on the weighted key term.