Abstract: A semiconductor device comprises: a semiconductor substrate comprising a first region and a second region; and first and second transistors on the first and second regions, respectively, wherein the first transistor comprises a first gate insulating layer pattern, the second transistor comprises a second gate insulating layer pattern, the first and second transistors both comprise a work function adjustment film pattern and a gate metal pattern, wherein the work function adjustment film pattern of the first transistor comprises the same material as the work function adjustment film pattern of the second transistor and the gate metal pattern of the first transistor comprises the same material as gate metal pattern of the second transistor, and a concentration of a metal contained in the first gate insulating layer pattern to adjust a threshold voltage of the first transistor is different from a concentration of the metal contained in the second gate insulating layer pattern to adjust a threshold voltage of the

Abstract: There is provided a semiconductor device comprising, at least one SRAM cell, wherein the SRAM cell includes a pull-up transistor, a pull-down transistor, and a pass-gate transistor, and an inversion-layer thickness (Tinv) of a gate stack of the pass-gate transistor is different from Tinv of a gate stack of the pull-up transistor and Tinv of a gate stack of the pull-down transistor.

Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.

Abstract: An integrated circuit device with metal gates including diffusion barrier layers and fabricating methods thereof are provided. The device may include a gate insulating film, a first conductivity type work function regulating film on the gate insulating film and a metal gate pattern on the first conductivity type work function regulating film. The device may include a cobalt film between the gate insulating film and the metal gate pattern to reduce diffusion from the metal gate pattern into the gate insulating film.

Abstract: A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a surface of a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the surface of the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion in a recessed portion of the substrate below the surface of the substrate, the resistor portion including a third polysilicon layer, and removing the first and second polysilicon layers from the first and second gate stack portions to expose the first and second gate oxide layers, wherein at least one of a dielectric layer and a stress liner cover a top surface of the resistor portion during removal of the first and second polysilicon layers.

Abstract: A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO2, ZrO2, Ta2O5, TiO2, SrTiO3 and (Ba,Sr)TiO3, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode.

Abstract: A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer.

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

Abstract: Semiconductor devices with replacement gate electrodes are formed with different materials in the work function layers. Embodiments include forming first and second removable gates on a substrate, forming first and second pairs of spacers on opposite sides of the first and second removable gates, respectively, forming a hardmask layer over the second removable gate, removing the first removable gate, forming a first cavity between the first pair of spacers, forming a first work function material in the first cavity, removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers, and forming a second work function material, different from the first work function material, in the second cavity.

Abstract: A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion on the substrate, the resistor portion including a third gate oxide layer and a third polysilicon layer on the third gate oxide layer, covering the resistor portion with a photoresist, removing respective first portions of the first and second polysilicon layers from the first and second gate stack portions, removing the photoresist from the resistor portion, and after removing the photoresist from the resistor portion, removing respective remaining portions of the first and second polysilicon layers from the first and second gate stack portions.

Abstract: A method for manufacturing a semiconductor device, comprising forming a metal gate of a transistor on a substrate by a replacement metal gate process, wherein an insulating layer is formed on the substrate adjacent the metal gate, forming a hard mask on the substrate including the insulating layer and the metal gate, the hard mask including an opening exposing the metal gate, performing a metal pull back process on the substrate to remove a predetermined depth of a top portion of the metal gate, depositing a protective layer on the substrate, including on the hard mask and on top of a remaining portion of the metal gate, and performing chemical mechanical polishing to remove the hard mask and the protective layer, wherein the protective layer formed on top of the remaining portion of the metal gate remains.

Abstract: A method for manufacturing a semiconductor device, comprising forming a first gate stack portion on a surface of a substrate, the first gate stack portion including a first gate oxide layer and a first polysilicon layer on the first gate oxide layer, forming a second gate stack portion on the surface of the substrate, the second gate stack portion including a second gate oxide layer and a second polysilicon layer on the second gate oxide layer, forming a resistor portion in a recessed portion of the substrate below the surface of the substrate, the resistor portion including a third polysilicon layer, and removing the first and second polysilicon layers from the first and second gate stack portions to expose the first and second gate oxide layers, wherein at least one of a dielectric layer and a stress liner cover a top surface of the resistor portion during removal of the first and second polysilicon layers.

Abstract: Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually. One of the metallic source gases may include an amino-group or an alkoxy-group and another metallic source gas may include neither an amino-group nor an alkoxy-group. A plasma may be produced in the reactor from the reactant gas.

Abstract: Provided is a metal-oxide semiconductor (MOS) transistor containing a metal gate pattern. The semiconductor device includes a p-channel metal-oxide semiconductor (PMOS) transistor including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first metal gate conductive film formed on the first insulating film, and a nitrogen diffusion blocking film formed between the first insulating film and the first metal gate conductive film, and an n-channel metal-oxide semiconductor (NMOS) transistor including the semiconductor substrate, a second insulating film formed on the semiconductor substrate, a second metal gate conductive film formed on the second insulating film, and a reaction blocking film formed of metal nitride and formed between the second insulating film and the second metal gate conductive film. According to the inventive concept, a reaction between a metal gate film and an insulating film may be minimized so as to result in a highly reliable MOS transistor.

Abstract: Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.

Abstract: A conventional plasma applied ALD apparatus has a problem in that physical shock is directly imposed on a substrate and a thin film thereby damaging the thin film. Further, many reports have said that since an apparatus for controlling plasma energy is not arranged well, the thin film is not formed uniformly due to plasma nonuniformity. Therefore, there is provided a remote plasma atomic layer deposition apparatus using a DC bias comprising: a reaction chamber having an inner space; a substrate supporting body on which a substrate on which a thin film is to be formed is loaded arranged at one side of the inner space of the reaction chamber; a remote plasma generating unit arranged outside of the reaction chamber to supply a remote plasma into the inner space of the reaction chamber; a DC bias unit controlling energy of the remote plasma; and a source gas supply unit supplying a source gas for forming the thin film into the reaction chamber.

Abstract: A method of manufacturing a memory device that improves electrical characteristics of an MIM capacitor using a zirconium oxide film (ZrO2) as a dielectric film includes: forming a lower metal electrode on a semiconductor substrate; forming a two or more-layered dielectric film including zirconium oxide films on the lower metal electrode; forming an upper metal electrode on the dielectric film; forming an MIM capacitor by patterning the upper metal electrode, the dielectric film, and the lower metal electrode; forming an interlayer insulating film covering the MIM capacitor; forming contacts in the insulating film; and performing heat treatment at a temperature range of 425 to 500° C.

Abstract: A method of forming a metallic oxide film using atomic layer deposition includes loading a substrate into a reactor, supplying a metallic source gas into the reactor and absorbing the metallic source gas onto the substrate, purging the remaining metallic source gas that does not react, with the substrate, and directly producing plasma of an N-group-containing oxide reactant gas in the reactor.

Abstract: Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually. One of the metallic source gases may include an amino-group or an alkoxy-group and another metallic source gas may include neither an amino-group nor an alkoxy-group. A plasma may be produced in the reactor from the reactant gas.