Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

Abstract: A semiconductor device is provided. The semiconductor device includes a first fin-type pattern on a substrate, a first interlayer insulating layer on the substrate, covering the first fin-type pattern and including a first trench, the first trench intersecting the first fin-type pattern, a first gate electrode on the first fin-type pattern, filling the first trench, an upper surface of the first gate electrode being coplanar with an upper surface of the first interlayer insulating layer, a capping layer extending along the upper surface of the first interlayer insulating layer and along the upper surface of the first gate electrode, and a second interlayer insulating layer on the capping layer, the second interlayer insulating layer including a material different from that of the capping layer.

Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a first direction, the first fin portion and the second fin portion being spaced apart from each other in the first direction, a field insulating layer between the first fin portion and the second fin portion and having an upper surface thereof lower than an upper surface of the first fin portion, a first metal gate extended in a second direction on the first fin portion and a silicon gate extended in the second direction on the field insulating layer and contacting the field insulating layer.

Abstract: A semiconductor device includes a first fin-shaped pattern and a second fin-shaped pattern arranged in a row in a direction, a trench between the first fin-shaped pattern and the second fin-shaped pattern, a field insulating layer filling a portion of the trench, an insulating line pattern crossing between the first fin-shaped pattern and the second fin-shaped pattern on the field insulating layer. A bottom surface of the insulating line pattern is lower than top surfaces of the first and second fin-shaped patterns.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed, which may improve the operating performance of a multi-gate transistor in a highly scaled integrated circuit device. The semiconductor device includes a first active fin unit protruding on a first region of a semiconductor substrate and extending along a first direction. The first active fin unit includes at least one first active fin having left and right profiles, which are symmetric to each other about a first center line perpendicular to a top surface of the semiconductor substrate on a cut surface perpendicular to the first direction. A second active fin unit protrudes on a second region of the semiconductor substrate and includes two second active fins, each having a left and right profiles, which are asymmetric to each other about a second center line perpendicular to the top surface of the semiconductor substrate on a cut surface.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract: A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction. The at least one second gate structure has a convex upper surface extending in the first direction and a second width in the second direction, the second width being greater than the first width.

Abstract: A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region.

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Abstract: A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO2, ZrO2, Ta2O5, TiO2, SrTiO3 and (Ba,Sr)TiO3, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode.

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.