Patents by Inventor Jui-Jen Wu

Jui-Jen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915733
    Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang
  • Publication number: 20240055031
    Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Publication number: 20230420041
    Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Publication number: 20230420013
    Abstract: A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.
    Type: Application
    Filed: May 18, 2022
    Publication date: December 28, 2023
    Inventors: Win-San KHWA, Jui-Jen WU, Jen-Chieh LIU, Meng-Fan CHANG
  • Publication number: 20230410926
    Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Patent number: 11829605
    Abstract: A memory device includes several normal memory circuits and a redundant memory circuit is disclosed. The several normal memory circuits include several normal memory arrays. The redundant memory circuit includes a redundant memory array. The several normal memory arrays share the redundant memory array. When a first normal memory cell of a first normal memory array of the several normal memory arrays is destructed, a first redundant memory cell of the redundant memory array replaces the first normal memory cell. When a second normal memory cell of a second normal memory array of the several normal memory arrays is destructed, a second redundant memory cell of the redundant memory array replaces the second normal memory cell.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 28, 2023
    Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., SILOAM HOLDINGS CO., LTD.
    Inventors: Jui-Jen Wu, Toshio Sunaga, Tzu-Hao Yang
  • Publication number: 20230377645
    Abstract: A memory device includes a set of word lines, a set of bit lines, a source line having first and second source line contacts, a set of transistors serially coupled between the first and second source line contacts of the source line, and a set of data storage elements. The set of transistors has gates coupled to corresponding word lines in the set of word lines. Each data storage element in the set of data storage elements is coupled between a common terminal of a corresponding pair of adjacent transistors in the set of transistors, and a corresponding bit line in the set of bit lines.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Inventors: Jui-Jen WU, Win-San KHWA, Jen-Chieh LIU, Meng-Fan CHANG
  • Publication number: 20230317132
    Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.
    Type: Application
    Filed: May 23, 2022
    Publication date: October 5, 2023
    Inventors: Jen-Chieh Liu, Jui-Jen Wu, Win-San Khwa, Yi-Lun Lu, Meng-Fan Chang
  • Publication number: 20230306245
    Abstract: A programming circuit includes a time difference converter circuit and a pulse generator circuit. The converter circuit is configured to receive a first pulse from a first neuron device and a second pulse from a second neuron device, and to output a time difference signal corresponding to a time difference between the first pulse and the second pulse. The pulse generator circuit includes an input coupled to the output of the time difference converter circuit to receive the time difference signal, and an output at which the pulse generator circuit is configured to output a program voltage corresponding to the time difference signal. The output of the pulse generator circuit is configured to be coupled to a synapse device coupled between the first neuron device and the second neuron device to program a weight value in the synapse device with the program voltage.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Inventors: Jen-Chieh LIU, Win-San KHWA, Jui-Jen WU, Meng-Fan CHANG
  • Publication number: 20230290402
    Abstract: A memory device that includes a memory array and a pre-charge selecting circuit is introduced. The memory array includes a plurality of memory cells that are coupled to a plurality of bit lines and a plurality of word lines, wherein the plurality of word lines are configured to receive an input vector. The pre-charge selecting circuit is configured to selectively pre-charge a selected bit line according to a value of the input vector. The pre-charge selecting circuit is configured to determine whether the value of the input vector is less than a predefined threshold, and generate a gated pre-charge signal to skip pre-charging the selected bit line in response to determining that the value of the input vector is less than the predefined threshold.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yen-Cheng Chiu, Je-Min Hung, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Publication number: 20230280976
    Abstract: Embodiments include monitoring a partial sum of a multiply accumulate calculation for certain conditions. When the certain conditions are met, a reduced read energy is used to read out memory contents instead of the regular read energy used. The reduced read energy may be obtained by reducing a pre-charge voltage, withholding a pre-charge voltage or providing a ground signal, and/or by reducing voltage hold times (i.e., reducing the time a pre-charge voltage is provided and/or discharged).
    Type: Application
    Filed: July 8, 2022
    Publication date: September 7, 2023
    Inventors: Win-San Khwa, Ping-Chun Wu, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Publication number: 20230267970
    Abstract: A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching devices coupled between the first and second data lines and first and second input terminals of the sense amplifier, third and fourth switching devices coupled between the first and second data lined and first and second nodes, fifth and sixth switching devices coupled between the first and second nodes and the reference voltage node, and first and second capacitive devices coupled between the first and second nodes and second and first input terminals. Each of the first through fourth switching devices is switched on and each of the fifth and sixth switching devices is switched off in a first operational mode, and each of the first through fourth switching devices is switched off and each of the fifth and sixth switching devices is switched on in a second operational mode.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Inventors: Jui-Jen WU, Win-San KWHA, Jen-Chieh LIU, Meng-Fan CHANG
  • Patent number: 11664790
    Abstract: A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Elia Ambrosi, Xinyu Bao, Meng-Fan Chang
  • Patent number: 11621024
    Abstract: A calibration device which is configured for calibrating a memory is provided. The calibration device includes an input terminal, a first pull-up circuit, and a first comparator. The input terminal is coupled to an external resistor. The first pull-up circuit is coupled to the input terminal, and configured to receive a power supply voltage. The first pull-up circuit includes a plurality of first pull-up units. The first pull-up units are coupled to each other in parallel. The first comparator is coupled to the input terminal. The first comparator is configured to receive a proportion voltage which is corresponding to the power supply voltage, and output a first control signal to the first pull-up units, such that a resistance of each of the first pull-up units is equal to a resistance of the external resistor.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 4, 2023
    Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., SILOAM HOLDINGS CO., LTD.
    Inventors: Jui-Jen Wu, Toshio Sunaga, Cho-Fan Chen
  • Publication number: 20230037044
    Abstract: A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.
    Type: Application
    Filed: February 2, 2022
    Publication date: February 2, 2023
    Inventors: Win-San KHWA, Jui-Jen WU, Jen-Chieh LIU, Meng-Fan Chang
  • Publication number: 20230028413
    Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.
    Type: Application
    Filed: January 17, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San KHWA, Jui-Jen WU, Jen-Chieh LIU, Meng-Fan Chang
  • Publication number: 20230010522
    Abstract: A method of storing a data into a memory storage having bit cells. The method includes identifying each of the binary one and the binary zero in the data as either a majority bit value or a minority bit value based on the probability of finding the binary one in the data or based on the probability of finding the binary zero in the data. In the method, a bit of the data is stored into the bit cell as the more preferred state if the bit of the data has the majority bit value, and a bit of the data is stored into the bit cell as the less preferred state if the bit of the data has the minority bit value.
    Type: Application
    Filed: May 5, 2022
    Publication date: January 12, 2023
    Inventors: Win-San KHWA, Jui Jen WU, Jen-Chieh LIU, Meng-Fan CHANG
  • Publication number: 20220415369
    Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.
    Type: Application
    Filed: April 14, 2022
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yen-Cheng Chiu, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Publication number: 20220301611
    Abstract: A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.
    Type: Application
    Filed: April 26, 2021
    Publication date: September 22, 2022
    Inventors: Jui-Jen WU, Toshio SUNAGA, Hsiu-Chun TSAI
  • Publication number: 20220300167
    Abstract: A memory device includes several normal memory circuits and a redundant memory circuit is disclosed. The several normal memory circuits include several normal memory arrays. The redundant memory circuit includes a redundant memory array. The several normal memory arrays share the redundant memory array. When a first normal memory cell of a first normal memory array of the several normal memory arrays is destructed, a first redundant memory cell of the redundant memory array replaces the first normal memory cell. When a second normal memory cell of a second normal memory array of the several normal memory arrays is destructed, a second redundant memory cell of the redundant memory array replaces the second normal memory cell.
    Type: Application
    Filed: April 26, 2021
    Publication date: September 22, 2022
    Inventors: Jui-Jen WU, Toshio SUNAGA, Tzu-Hao YANG