Abstract: A memory device includes a memory array, a bit line driving circuit, a word line driving circuit, a read/write circuit, a controller, and a reference driving circuit. The memory array includes several memory units. The bit line driving circuit is configured to interpret a memory bit address and to drive a bit line. The word line driving circuit is configured to interpret a memory word address and to drive a word line. The read/write circuit is configured to read, set, or reset the memory units. The controller is configured to switch the memory array to work in a single memory unit mode or a dual memory unit mode. The reference driving circuit is configured to drive a reference line, wherein the reference line comprises several reference units, and the reference line and the reference units are located in the memory array.

Abstract: A sensing-amplifier device includes a first input terminal, a second input terminal, a reference unit, and a sense amplifier. The reference unit is configured to provide a reference signal. The switching unit is selectively coupled to the first input terminal, the second input terminal, and a reference unit. The sense amplifier includes two terminals. The two terminals of the sense amplifier are coupled to the first input terminal and the second input terminal respectively by switching of the switching unit so as to operate in a twin memory unit mode, or one terminal of the sense amplifier is coupled to the first input terminal or the second input terminal and the other terminal of the sense amplifier is coupled to the reference unit by switching of the switching unit so as to operate in a single memory unit mode.

Abstract: A memory device includes a memory array, a bit line driving circuit, a word line driving circuit, a read/write circuit, a controller, and a reference driving circuit. The memory array includes several memory units. The bit line driving circuit is configured to interpret a memory bit address and to drive a bit line. The word line driving circuit is configured to interpret a memory word address and to drive a word line. The read/write circuit is configured to read, set, or reset the memory units. The controller is configured to switch the memory array to work in a single memory unit mode or a dual memory unit mode. The reference driving circuit is configured to drive a reference line, wherein the reference line comprises several reference units, and the reference line and the reference units are located in the memory array.

Abstract: A sensing-amplifier device includes a first input terminal, a second input terminal, a reference unit, and a sense amplifier. The reference unit is configured to provide a reference signal. The switching unit is selectively coupled to the first input terminal, the second input terminal, and a reference unit. The sense amplifier includes two terminals. The two terminals of the sense amplifier are coupled to the first input terminal and the second input terminal respectively by switching of the switching unit so as to operate in a twin memory unit mode, or one terminal of the sense amplifier is coupled to the first input terminal or the second input terminal and the other terminal of the sense amplifier is coupled to the reference unit by switching of the switching unit so as to operate in a single memory unit mode.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A memory device includes first and second memory arrays, first and second bit line driving circuits, first and second word line driving circuits, a read/write circuit, a controller, and first and second reference driving circuits. The first and second memory arrays include several memory units. The first and second bit line driving circuits are configured to interpret a memory bit address and drive a bit line. The first and second word line driver circuits are configured to interpret the memory word address and drive the word line. The read/write circuit is configured to read, set or reset the memory units. The controller is configured to switch the first and second memory arrays to work in a single memory unit mode or a dual memory unit mode. The first and second reference driving circuits are configured to drive reference rows.

Abstract: A memory driving circuit is disclosed herein. The memory driving circuit includes a programmable current source, a reference voltage generation unit and a voltage comparator unit, The programmable current source generates a second current according to a first current. The second current flows into a memory cell, and produces a device voltage at the input of the memory cell. The reference voltage generation unit generates a crystal voltage. The voltage comparator unit compares the device voltage with the crystal voltage and sends out a control signal to control the programmable current source. The first current and the second current are adjusted by the control signal so that the shape of the current pulse of SET operation to the memory cell is well controlled.

Abstract: A memory driving circuit is disclosed herein. The memory driving circuit includes a programmable current source, a reference voltage generation unit and a voltage comparator unit, The programmable current source generates a second current according to a first current. The second current flows into a memory cell, and produces a device voltage at the input of the memory cell. The reference voltage generation unit generates a crystal voltage. The voltage comparator unit compares the device voltage with the crystal voltage and sends out a control signal to control the programmable current source. The first current and the second current are adjusted by the control signal so that the shape of the current pulse of SET operation to the memory cell is well controlled.

Abstract: A non-volatile memory cell and a non-volatile memory device are provided. The non-volatile memory cell includes a latch structure, a first read/write circuit, a first memristor, a second read/write circuit and a second memristor. The first read/write circuit controls a writing operation of the first memristor. The second read/write circuit controls a writing operation of the second memristor. When a restore operation is performed, the data in the latch structure is restored by using the resistance difference between the first memristor and the second memristor. The non-volatile device of the invention combines the advantages of fast memory unit and non-volatile memory, and it may work at a high speed and retain data when powered off.

Abstract: A non-volatile memory device includes plural non-memory cells. Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a second memristor and a third switch. The control terminal of the first switch is coupled to a word line. The first memristor is provided with a first impedance. The control terminal of the second switch is coupled to the word line. The second memristor is provided with a second impedance. The first switch, the first memristor, the second switch and the second memristor are serially connected between a bit line and an inverted bit line in an alternate manner. The third switch is used for configuring the first impedance and the second impedance. The non-volatile memory device provided by the disclosure has a characteristic of quick access and the data stored therein does not require a dynamic update.

Abstract: A non-volatile memory cell and a non-volatile memory device are provided. The non-volatile memory cell includes a latch structure, a first read/write circuit, a first memristor, a second read/write circuit and a second memristor. The first read/write circuit controls a writing operation of the first memristor. The second read/write circuit controls a writing operation of the second memristor. When a restore operation is performed, the data in the latch structure is restored by using the resistance difference between the first memristor and the second memristor. The non-volatile device of the invention combines the advantages of fast memory unit and non-volatile memory, and it may work at a high speed and retain data when powered off.

Abstract: A memory driving circuit includes a current source configured to output a second current, a first switching unit configured to undergo switching to connect to the current source selectively to output the second current, a voltage generating unit configured to provide a reference voltage, a capacitive energy storage unit configured to store energy according to the reference voltage, a third switching unit configured to undergo switching to connect the voltage generating unit and the capacitive energy storage unit selectively, a second switching unit configured to undergo switching to connect the capacitive energy storage unit selectively to output a third current, and a current output terminal configured to output the second current, the third current, or the sum of the second current and the third current.

Abstract: A memory device includes a memory array, a word line driver, and source drivers. The memory array includes memory units. The memory units arranged in the same column are coupled to corresponding bit line. The memory units arranged in the same row are coupled to corresponding word line. The memory units arranged in the rows are divided into N groups, in which N is an integer greater than or equal to 2. The word line driver is configured to selectively enable the word lines. Source drivers are coupled to the memory units in the groups respectively and configured to output N source control signals. When any word line in a first group is enabled, the source control signals corresponding to the first group and a second group of which the sequence for read-write operation is next to the first group are controlled at a select level by corresponding source drivers.

Abstract: A non-volatile storage device adopt memristors to store data and uses fewer transistors to realize the same circuit function, whereby to decrease the chip area and reduce the time and energy spent in initiating the device. Further, the non-volatile storage device disposes appropriate electronic elements in the spacing between adjacent memristors to meet the layout design rule and achieve high space efficiency in the chip lest the space between memristors be wasted.

Abstract: A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit.

Abstract: A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point.

Abstract: A sensing margin expanding scheme for a memory and a method therefor is disclosed. A first terminal of a first capacitor is coupled to a bit line. A first terminal of a second capacitor is coupled to a reference voltage. In a first phase, the controller controls a first common switch and a second common switch to store the voltage difference between the bit line and the reference voltage to the first capacitor and the second capacitor. In a second phase, controlling the first common switch and the second common switch to open the first terminal of the first capacitor and the second terminal of the second capacitor and open the second terminal of the first capacitor and the first terminal of the second capacitor, and then coupling the second terminal of the first capacitor and the second terminal of the second capacitor to a common voltage.

Abstract: A sensing margin expanding scheme for a memory and a method therefor is disclosed. A first terminal of a first capacitor is coupled to a bit line. A first terminal of a second capacitor is coupled to a reference voltage. In a first phase, the controller controls a first common switch and a second common switch to store the voltage difference between the bit line and the reference voltage to the first capacitor and the second capacitor. In a second phase, controlling the first common switch and the second common switch to open the first terminal of the first capacitor and the second terminal of the second capacitor and open the second terminal of the first capacitor and the first terminal of the second capacitor, and then coupling the second terminal of the first capacitor and the second terminal of the second capacitor to a common voltage.

Abstract: A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.

Abstract: A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and the word line, a first switch electrically connected to the first voltage supply node and a bulk electrode of the second transistor, and a second switch electrically connected to the second voltage supply node and the bulk electrode of the second transistor.