Abstract: A non-volatile storage device adopt memristors to store data and uses fewer transistors to realize the same circuit function, whereby to decrease the chip area and reduce the time and energy spent in initiating the device. Further, the non-volatile storage device disposes appropriate electronic elements in the spacing between adjacent memristors to meet the layout design rule and achieve high space efficiency in the chip lest the space between memristors be wasted.

Abstract: A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit.

Abstract: A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point.

Abstract: A sensing margin expanding scheme for a memory and a method therefor is disclosed. A first terminal of a first capacitor is coupled to a bit line. A first terminal of a second capacitor is coupled to a reference voltage. In a first phase, the controller controls a first common switch and a second common switch to store the voltage difference between the bit line and the reference voltage to the first capacitor and the second capacitor. In a second phase, controlling the first common switch and the second common switch to open the first terminal of the first capacitor and the second terminal of the second capacitor and open the second terminal of the first capacitor and the first terminal of the second capacitor, and then coupling the second terminal of the first capacitor and the second terminal of the second capacitor to a common voltage.

Abstract: A sensing margin expanding scheme for a memory and a method therefor is disclosed. A first terminal of a first capacitor is coupled to a bit line. A first terminal of a second capacitor is coupled to a reference voltage. In a first phase, the controller controls a first common switch and a second common switch to store the voltage difference between the bit line and the reference voltage to the first capacitor and the second capacitor. In a second phase, controlling the first common switch and the second common switch to open the first terminal of the first capacitor and the second terminal of the second capacitor and open the second terminal of the first capacitor and the first terminal of the second capacitor, and then coupling the second terminal of the first capacitor and the second terminal of the second capacitor to a common voltage.

Abstract: A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.

Abstract: A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and the word line, a first switch electrically connected to the first voltage supply node and a bulk electrode of the second transistor, and a second switch electrically connected to the second voltage supply node and the bulk electrode of the second transistor.

Abstract: A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit.

Abstract: A multiple power domain circuit includes a trigger circuit, a high threshold voltage circuit electrically connected to an output terminal of the trigger circuit, and a low threshold voltage circuit electrically connected to the output terminal of the trigger circuit and an output terminal of the high threshold voltage circuit. The low threshold voltage circuit comprises a pulse generator electrically connected to the output terminal of the trigger circuit, and an inverter electrically connected to an output terminal of the pulse generator, and the output terminal of the high threshold voltage circuit.

Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.

Abstract: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

Abstract: A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point.

Abstract: A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and the word line, a first switch electrically connected to the first voltage supply node and a bulk electrode of the second transistor, and a second switch electrically connected to the second voltage supply node and the bulk electrode of the second transistor.

Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.

Abstract: A multiple power domain circuit includes a trigger circuit, a high threshold voltage circuit electrically connected to an output terminal of the trigger circuit, and a low threshold voltage circuit electrically connected to the output terminal of the trigger circuit and an output terminal of the high threshold voltage circuit. The low threshold voltage circuit comprises a pulse generator electrically connected to the output terminal of the trigger circuit, and an inverter electrically connected to an output terminal of the pulse generator, and the output terminal of the high threshold voltage circuit.

Abstract: A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line.

Abstract: A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.

Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Abstract: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

Abstract: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.