Abstract: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract: A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.

Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line.

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-line connected to the SRAM cell. A negative-voltage generator is coupled to, and configured to output a negative voltage to, the bit-line, wherein the negative-voltage generator is so configured that the negative voltage decreases in response to a decrease in the first positive power supply voltage and increases in response to an increase in the first positive supply voltage.

Abstract: A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit.

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.

Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Abstract: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line.

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-line connected to the SRAM cell. A negative-voltage generator is coupled to, and configured to output a negative voltage to, the bit-line, wherein the negative-voltage generator is so configured that the negative voltage decreases in response to a decrease in the first positive power supply voltage and increases in response to an increase in the first positive supply voltage.

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.

Abstract: A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.

Abstract: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.