Abstract: A calibration device which is configured for calibrating a memory is provided. The calibration device includes an input terminal, a first pull-up circuit, and a first comparator. The input terminal is coupled to an external resistor. The first pull-up circuit is coupled to the input terminal, and configured to receive a power supply voltage. The first pull-up circuit includes a plurality of first pull-up units. The first pull-up units are coupled to each other in parallel. The first comparator is coupled to the input terminal. The first comparator is configured to receive a proportion voltage which is corresponding to the power supply voltage, and output a first control signal to the first pull-up units, such that a resistance of each of the first pull-up units is equal to a resistance of the external resistor.

Abstract: A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.

Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Abstract: A method of storing a data into a memory storage having bit cells. The method includes identifying each of the binary one and the binary zero in the data as either a majority bit value or a minority bit value based on the probability of finding the binary one in the data or based on the probability of finding the binary zero in the data. In the method, a bit of the data is stored into the bit cell as the more preferred state if the bit of the data has the majority bit value, and a bit of the data is stored into the bit cell as the less preferred state if the bit of the data has the minority bit value.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.

Abstract: A memory device includes several normal memory circuits and a redundant memory circuit is disclosed. The several normal memory circuits include several normal memory arrays. The redundant memory circuit includes a redundant memory array. The several normal memory arrays share the redundant memory array. When a first normal memory cell of a first normal memory array of the several normal memory arrays is destructed, a first redundant memory cell of the redundant memory array replaces the first normal memory cell. When a second normal memory cell of a second normal memory array of the several normal memory arrays is destructed, a second redundant memory cell of the redundant memory array replaces the second normal memory cell.

Abstract: A calibration device which is configured for calibrating a memory is provided. The calibration device includes an input terminal, a first pull-up circuit, and a first comparator. The input terminal is coupled to an external resistor. The first pull-up circuit is coupled to the input terminal, and configured to receive a power supply voltage. The first pull-up circuit includes a plurality of first pull-up units. The first pull-up units are coupled to each other in parallel. The first comparator is coupled to the input terminal. The first comparator is configured to receive a proportion voltage which is corresponding to the power supply voltage, and output a first control signal to the first pull-up units, such that a resistance of each of the first pull-up units is equal to a resistance of the external resistor.

Abstract: A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.

Abstract: A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Abstract: A random number generator that includes control circuit, an oscillation circuit, a dynamic header circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The dynamic header circuit generates a bias voltage based on the configuration of the bias control signal. The oscillation circuit generates an oscillation signal based on the bias voltage. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Abstract: Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The reference voltage generation circuit comprises a reference resistor and is used to generate a reference signal according to the first signal. The first switch is coupled to a memory resistor and is used to generate a drive signal according to the first signal so as to set a resistance value of the memory resistor. When the input signal is decreased and a resistance value of the memory resistor is greater than a resistance value of the reference resistor, the time when the drive signal is decreased is greater than the time when the reference signal is decreased.

Abstract: A memory driving device, comprising a switch, a voltage setting circuit, and a bias control circuit. The switch is coupled to a memory at a node. The voltage setting circuit is coupled to the switch and configured to provide a set signal during a first period to turn on the switch, so as to generate current flowing through the switch to the memory unit. The bias control circuit is respectively coupled to the switch and the node, and, during a second period, continuously provides a bias signal to control the switch so as to adaptively adjust a value of the setting current of the switch. The configuration setting terminal is coupled to the voltage setting circuit and the bias control circuit to control the first and the second period.

Abstract: A memory driving device, comprising a switch, a voltage setting circuit, and a bias control circuit. The switch is coupled to a memory at a node. The voltage setting circuit is coupled to the switch and configured to provide a set signal during a first period to turn on the switch, so as to generate current flowing through the switch to the memory unit. The bias control circuit is respectively coupled to the switch and the node, and, during a second period, continuously provides a bias signal to control the switch so as to adaptively adjust a value of the setting current of the switch. The configuration setting terminal is coupled to the voltage setting circuit and the bias control circuit to control the first and the second period.

Abstract: Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The reference voltage generation circuit comprises a reference resistor and is used to generate a reference signal according to the first signal. The first switch is coupled to a memory resistor and is used to generate a drive signal according to the first signal so as to set a resistance value of the memory resistor. When the input signal is decreased and a resistance value of the memory resistor is greater than a resistance value of the reference resistor, the time when the drive signal is decreased is greater than the time when the reference signal is decreased.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A memory device includes a memory array, write drivers and a controller. The memory array includes a plurality of memory units respectively arranged in a plurality of bit lines. The write drivers generate a plurality of write bit signals respectively inputted to the bit lines. The controller provides a voltage mode control signal and a current mode control signal. The controller is electrically coupled to the write drivers. Each of the write drivers generates a respective write bit signal of each of the write drivers according to the voltage mode control signal and the current mode control signal. When each of the memory units is in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers. When each of the memory units is in a reset state, the controller outputs the voltage mode control signal to the write drivers.

Abstract: A memory device includes a memory array, write drivers and a controller. The memory array includes a plurality of memory units respectively arranged in a plurality of bit lines. The write drivers generate a plurality of write bit signals respectively inputted to the bit lines. The controller provides a voltage mode control signal and a current mode control signal. The controller is electrically coupled to the write drivers. Each of the write drivers generates a respective write bit signal of each of the write drivers according to the voltage mode control signal and the current mode control signal. When each of the memory units is in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers. When each of the memory units is in a reset state, the controller outputs the voltage mode control signal to the write drivers.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A sensing-amplifier device includes a first input terminal, a second input terminal, a reference unit, and a sense amplifier. The reference unit is configured to provide a reference signal. The switching unit is selectively coupled to the first input terminal, the second input terminal, and a reference unit. The sense amplifier includes two terminals. The two terminals of the sense amplifier are coupled to the first input terminal and the second input terminal respectively by switching of the switching unit so as to operate in a twin memory unit mode, or one terminal of the sense amplifier is coupled to the first input terminal or the second input terminal and the other terminal of the sense amplifier is coupled to the reference unit by switching of the switching unit so as to operate in a single memory unit mode.