Patents by Inventor Jui-Jen Wu
Jui-Jen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7535788Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.Type: GrantFiled: December 8, 2006Date of Patent: May 19, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Jen Wu, Kun-Lung Chen, Hung-Jen Liao, Yung-Lung Lin, Chen Yen-Huei, Dao-Ping Wang
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Patent number: 7505319Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.Type: GrantFiled: January 31, 2007Date of Patent: March 17, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Yung-Lung Lin, Yen-Huei Chen, Dao-Ping Wang
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Patent number: 7468903Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.Type: GrantFiled: November 13, 2006Date of Patent: December 23, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dao-Ping Wang, Hung-Jen Liao, Kun Lung Chen, Yung-Lung Lin, Jui-Jen Wu, Chen Yen-Huei
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Patent number: 7466581Abstract: An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.Type: GrantFiled: March 2, 2007Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yen-Huei Chen, Jui-Jen Wu, Ping-Wei Wang
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Publication number: 20080217734Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Inventors: Yung-Lung Lin, Jui-Jen Wu, Shine Chung, Fu-Lung Hsuen
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Publication number: 20080212353Abstract: An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.Type: ApplicationFiled: March 2, 2007Publication date: September 4, 2008Inventors: Huai-Ying Huang, Yen-Huei Chen, Jui-Jen Wu, Ping-Wei Wang
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Publication number: 20080191798Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.Type: ApplicationFiled: February 12, 2007Publication date: August 14, 2008Inventors: Shao-Yu Chou, Yen-Huei Chen, Jui-Jen Wu, Gary Chan
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Publication number: 20080184064Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Jen Wu, Yung-Lung Lin, Yen-Huei Chen, Dao-Ping Wang
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Publication number: 20080158939Abstract: A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.Type: ApplicationFiled: January 2, 2007Publication date: July 3, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Huei Chen, Hung-Jen Liao, Kun-Lung Chen, Jui-Jen Wu, Yung-Lung Lin, Dao-Ping Wang
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Publication number: 20080144419Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Inventors: Jui-Jen Wu, Kun-Lung Chen, Hung-Jen Liao, Yung-Lung Lin, Chen Yen-Huei, Dao-Ping Wang
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Publication number: 20080137449Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Inventors: Jui-Jen Wu, Kun-Lung Chen, Hung-Jen Liao, Yung-Lung Lin, Chen Yen-Huei, Dao-Ping Wang
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Patent number: 7362647Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device and a second terminal coupled to the node of the integrated circuit module for controlling the switch device to pass the supply voltage to the node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module, the switch control module having at least one capacitor for selectively discharging the node, thereby creating the substantial voltage drop for the supply voltage across the switch device.Type: GrantFiled: September 30, 2006Date of Patent: April 22, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jui-Jen Wu
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Publication number: 20080013394Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device and a second terminal coupled to the node of the integrated circuit module for controlling the switch device to pass the supply voltage to the node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module, the switch control module having at least one capacitor for selectively discharging the node, thereby creating the substantial voltage drop for the supply voltage across the switch device.Type: ApplicationFiled: September 30, 2006Publication date: January 17, 2008Inventor: Jui-Jen Wu
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Patent number: 7319355Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.Type: GrantFiled: January 3, 2006Date of Patent: January 15, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Jen Wu, Yung-Lung Lin
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Patent number: 7271644Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.Type: GrantFiled: January 10, 2006Date of Patent: September 18, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Lung Lin, Jui-Jen Wu, Hung-Jen Liao
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Publication number: 20070159231Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.Type: ApplicationFiled: January 10, 2006Publication date: July 12, 2007Inventors: Yung-Lung Lin, Jui-Jen Wu, Hung-Jen Liao
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Publication number: 20070152726Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.Type: ApplicationFiled: January 3, 2006Publication date: July 5, 2007Inventors: Jui-Jen Wu, Yung-Lung Lin
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Publication number: 20060232904Abstract: A sensing circuit is disclosed for sensing a programming state of an electrical fuse, comprising. An electrical fuse is coupled to a supply voltage. A first transistor is serially coupled between the electrical fuse and a complementary supply voltage. An inverter sense amplifier is coupled to a node between the electrical fuse and the first transistor for outputting a logic signal whose value is determined based on a comparison between a resistance of the electrical fuse and a predetermined reference resistance. A bias circuit applies a bias independent of variation of the first voltage to a gate of the first transistor, such that the predetermined reference resistance is substantially insensitive to the variation of the first voltage.Type: ApplicationFiled: April 13, 2005Publication date: October 19, 2006Inventors: Jui-Jen Wu, Yung-Lung Lin
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Patent number: 7019534Abstract: A fuse detection circuit has; a fuse (102) under detection to produce a first voltage in the first arm in response to a read signal; a reference fuse (108) to produce a second voltage in response to the read signal; a sensing circuit (124) to sense the first voltage and the second voltage as status value data of the fuse under detection; a latch circuit (136) to keep the data in the sensing circuit; and a timing control circuit (138) to turn off the fuse bridge circuit independently of the read signal.Type: GrantFiled: March 26, 2004Date of Patent: March 28, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Jui-Jen Wu
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Publication number: 20050212527Abstract: A fuse detection circuit has; a fuse (102) under detection to produce a first voltage in the first arm in response to a read signal; a reference fuse (108) to produce a second voltage in response to the read signal; a sensing circuit (124) to sense the first voltage and the second voltage as status value data of the fuse under detection; a latch circuit (136) to keep the data in the sensing circuit; and a timing control circuit (138) to turn off the fuse bridge circuit independently of the read signal.Type: ApplicationFiled: March 26, 2004Publication date: September 29, 2005Inventor: Jui-Jen Wu