Patents by Inventor Jui Li

Jui Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250130069
    Abstract: The disclosure provides an update image map method applied to a vehicle, which comprising the following steps of: receiving a message used to determine whether conditions for updating an image map are met; determining whether the conditions for updating the image map are met according to the message; when it is determined that the conditions for updating the image map are met, receiving a vehicle information and capturing images from one or more cameras; processing the images based on lens characteristics of the one or more cameras and the vehicle information; and writing the processed images to a corresponding location on the image map based on the received vehicle information.
    Type: Application
    Filed: September 12, 2024
    Publication date: April 24, 2025
    Inventors: Jui-Li Chen, Guan-you Lin, Chia-Ling Cheng, Tse-Min Chen
  • Patent number: 12274088
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: April 8, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li
  • Publication number: 20250111639
    Abstract: This invention provides a method for detecting object, which comprises receiving an image; and executing a deep neural network architecture for the image to obtain one or more object bounding box, wherein the deep neural network architecture comprises a two-dimensional discrete wavelet transform.
    Type: Application
    Filed: September 3, 2024
    Publication date: April 3, 2025
    Inventors: Jun-Yao Zhong, Bo-Yu Chen, Jui-Li Chen, Tse-Min Chen
  • Publication number: 20250101572
    Abstract: Apparatus and methods for multi-cathode barrier seed deposition for high aspect ratio features in a physical vapor deposition (PVD) process are provided herein. In some embodiments, a PVD chamber includes a pedestal disposed within a processing region of the PVD chamber. The pedestal rotates with a workpiece on it. The PVD chamber includes a lid assembly includes a first target and a second target of a same target material, where a first surface of the first target defines a first zone of the processing region a first distance from the upper surface of the pedestal, and a second surface of the second target defines a second zone of the processing region a second distance from the plane of the upper surface of the pedestal. A system controller is configured to simultaneously control a first voltage bias for the first target and a second voltage bias for the second target.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Harish Y. PENMETHSA, Ming-Jui LI
  • Publication number: 20250086959
    Abstract: A method for object and key-point detection, comprising: receiving an image, executing a deep neural network architecture for the image to obtain one or more object bounding boxes; executing the deep neural network architecture for the one or more object bounding boxes to obtain one or more key-point positions corresponding to the one or more object bounding boxes; and outputting the one or more object bounding boxes and the one or more key-point positions.
    Type: Application
    Filed: July 18, 2024
    Publication date: March 13, 2025
    Inventors: Jun-Yao Zhong, Bo-Yu Chen, Jui-Li Chen, Tse-Min Chen
  • Publication number: 20250058791
    Abstract: This disclosure provides a method for determining visual and auditory attentiveness of vehicle driver, which comprises: determining a visual attentiveness of a driver according to an image captured by a camera installed inside the vehicle; determining a recognition attentiveness of the driver according to sounds obtained by a microphone installed inside the vehicle; deciding whether to issue a reminder to the driver based on the visual attentiveness and the recognition attentiveness of the driver; when it is necessary to remind the driver after determining the driver's visual and recognition attentiveness, one or a combination of reminder steps will be executed; the reminder steps comprising: issuing a visual reminder by a display device in the vehicle; and issuing a auditory reminder by a speaker in the vehicle.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 20, 2025
    Inventors: Peter Chondro, Jun-Yao Zhong, Bo-Yu Chen, Tse-Min Chen, Jui-Li Chen
  • Patent number: 12206148
    Abstract: The invention discloses a filter device. The filter device comprises a substrate, at least one transmission conductor, and a reference conductor having a slotted structure. The substrate is provided at a first surface thereof with the transmission conductor, and provided at a second surface thereof with the reference conductor. The slotted structure comprises a frame portion, a slotted portion, and a hollow portion. The slotted portion surrounds the frame portion, and the hollow portion is formed in the frame portion. At least one impedance unit is configured on the frame portion. The equivalent filter circuit of the filter device is formed between the transmission conductor, the slotted structure, the reference conductor, and the impedance unit. Thereby, the equivalent filter circuit absorbs at least one noise at at least one specific frequency by the impedance unit to avoid the noise reflected to affect the transmission quality of signal.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: January 21, 2025
    Assignee: National Taiwan University
    Inventors: Tzong-Lin Wu, Hsu-Wei Liu, Chi-Hsuan Cheng, Po-Jui Li
  • Patent number: 12195843
    Abstract: Apparatus and methods for multi-cathode barrier seed deposition for high aspect ratio features in a physical vapor deposition (PVD) process are provided herein. In some embodiments, a PVD chamber includes a pedestal disposed within a processing region of the PVD chamber. The pedestal rotates with a workpiece on it. The PVD chamber includes a lid assembly includes a first target and a second target of a same target material, where a first surface of the first target defines a first zone of the processing region a first distance from the upper surface of the pedestal, and a second surface of the second target defines a second zone of the processing region a second distance from the plane of the upper surface of the pedestal. A system controller is configured to simultaneously control a first voltage bias for the first target and a second voltage bias for the second target.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 14, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Harish V. Penmethsa, Ming-Jui Li
  • Publication number: 20250008725
    Abstract: A semiconductor device includes a substrate, a bit line structure formed over and protruding from the substrate, a spacer structure formed on and extending along sidewall of the bit line structure, and a landing pad disposed on the bit line structure and covering the slope. The spacer structure includes a first segment near a top of the spacer structure with a slope and a second segment beneath the first segment. A first segment consists of a first spacer layer contacting the bit line structure and a third spacer layer contacting the first spacer layer. A second segment consists of the first spacer layer contacting the bit line structure, a second spacer layer contacting the first spacer layer, and the third spacer layer contacting the second spacer layer, and the second segment is capped with the first segment.
    Type: Application
    Filed: September 11, 2024
    Publication date: January 2, 2025
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI, Chih-Yu YEN
  • Publication number: 20240407155
    Abstract: A semiconductor memory device includes a substrate, a memory cell contact formed over the substrate, a bit line conductive structure formed over the substrate and a dielectric spacer located between the memory cell contact and the bit line conductive structure. The dielectric spacer includes an air gap having a rectangular cross-section, and the rectangular cross-section has a height H and a width W, wherein a H/W ratio is equal to or greater than 40.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Kuo Chung HSU, En-Jui LI
  • Publication number: 20240407153
    Abstract: The present disclosure provides a memory device and the forming method thereof. The memory device includes a bit line on a substrate, a multilayer spacer covering the bit line, a low-k dielectric layer and an air gap interposed in the multilayer spacer, and a cell contact adjacent to the multilayer spacer. The multilayer spacer, the low-k dielectric layer, and the air gap are disposed between the bit line and the cell contact. The top surface of the low-k dielectric layer is lower than a top surface of the bit line. The air gap is above the low-k dielectric layer, and an orthogonal projection of the air gap onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Inventors: Kuo Chung HSU, En-Jui LI
  • Patent number: 12159916
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20240395051
    Abstract: The present invention provides a driving assistance system and a driving assistance computation method that utilize a deep neural network architecture to achieve object detection and semantic segmentation functionalities in a single inference of the same model.
    Type: Application
    Filed: January 9, 2024
    Publication date: November 28, 2024
    Applicant: AutoSys (TW) Co., Ltd.
    Inventors: Han-Wei Huang, Bo-Yu Chen, Tse-Min Chen, Jui-Li Chen
  • Publication number: 20240387678
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20240372000
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 12127392
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: October 22, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li, Chih-Yu Yen
  • Publication number: 20240347374
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: KUO-CHUNG HSU, EN-JUI LI
  • Publication number: 20240347375
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate having an active region and a shallow trench isolation (STI) adjacent to the active region of the substrate. The STI includes a charge trapping layer and a liner disposed between the charge trapping layer and the active region of the substrate, wherein the charge trapping layer is doped with an impurity.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: KUO-CHUNG HSU, EN-JUI LI
  • Publication number: 20240347502
    Abstract: Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Mike Breeden, Victor Wang, Andrew Kummel, Ming-Jui Li, Muhannad Bakir, Jonathan Hollin, Nyi Myat Khine Linn, Charles H. Winter
  • Patent number: 12107935
    Abstract: The present disclosure relates to a system, a method and a computer-readable medium for notification of a live streaming program. The method includes obtaining a list of users related to the live streaming program, obtaining a first contribution score of a first user in the list of users, and transmitting a first notification request for notifying the first user about the live streaming program according to the first contribution score. The first contribution score is determined according to a behavior of the first user. The present disclosure can result in a more reliable notification, which may further improve the operation of a live streaming platform.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: October 1, 2024
    Assignee: 17LIVE JAPAN INC.
    Inventors: Hong Dian Chen, Hsing Yu Tsai, Jui Li