Patents by Inventor Jui Li

Jui Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190356535
    Abstract: Concepts and technologies directed to network fault originator identification for virtual network infrastructure are disclosed herein. Embodiments can include a control system that is communicatively coupled with network infrastructure. The control system can include a processor and memory that, upon execution, causes the control system to perform operations. The operations can include determining, based on a source ticket, a network fault condition associated with the network infrastructure. The operations can further include identifying, from the source ticket, a trap set and an alarm set that are associated with origination of the network fault condition. The operations can include the control system collecting network event data from the network infrastructure prior to a polling time of a fault reporting schedule; determining that a qualified source ticket should be created; and generating the qualified source ticket based on the network event data.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Applicant: AT&T Intellectual Property I, L.P.
    Inventors: Wen-Jui Li, Tsong-Ho Wu, Wai Sum Lai, Zosim Kanevsky, Jun-Min Liu
  • Patent number: 10484265
    Abstract: An IP network topology update system may update IP network topology in near real-time and on-demand with minimum overheads. It identifies likely impact area (e.g., layer 2 or layer 3), objects (e.g., link or node such a device), and timing (e.g., what topology objects located where or when the topology update process should be performed) in the IP Layer 3 network and its underlying SDN Layer 2 network under virtualized networking infrastructure as candidates of impacts for topology update.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 19, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Tsong-Ho Wu, Wen-Jui Li, Wai Lai
  • Publication number: 20190334937
    Abstract: A method and an apparatus for detecting a port scan in a network are disclosed. For example, the method extracts statistics from a message, detects the port scan for a source internet protocol address, determines whether a port scan record exists for the source internet protocol address, creates a port scan record for the source internet protocol address that is extracted when the port scan record does not exist, determines an elapsed time when the port scan record does exist, wherein the elapsed time is determined as a difference between the time stamp that is extracted and a recorded time stamp, sets the recorded time stamp to be the extracted time stamp when the elapsed time is less than an intra-scan time, and determines the port scan has ended for the source internet protocol address when the elapsed time is not less than the intra-scan time.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Inventors: Wai Sum Lai, Andrew Egan, Wen-Jui Li
  • Patent number: 10396419
    Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 27, 2019
    Assignee: National Taiwan University
    Inventors: Tzong-Lin Wu, Po-Jui Li, Ying-Cheng Tseng, Chi-Hsuan Cheng
  • Publication number: 20190252539
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10348749
    Abstract: A method and an apparatus for detecting a port scan in a network are disclosed. For example, the method extracts statistics from a message, detects the port scan for a source internet protocol address, determines whether a port scan record exists for the source internet protocol address, creates a port scan record for the source internet protocol address that is extracted when the port scan record does not exist, determines an elapsed time when the port scan record does exist, wherein the elapsed time is determined as a difference between the time stamp that is extracted and a recorded time stamp, sets the recorded time stamp to be the extracted time stamp when the elapsed time is less than an intra-scan time, and determines the port scan has ended for the source internet protocol address when the elapsed time is not less than the intra-scan time.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 9, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Wai Sum Lai, Andrew Egan, Wen-Jui Li
  • Patent number: 10312149
    Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate, and the substrate includes a first region and a second region. The FinFET structure includes a first plurality of fin structures formed on the first region and a second plurality of fin structures formed on the second region. A density of the first plurality of fin structures is greater than a density of the second plurality of fin structures. The FinFET structure also includes a plurality of protruding structures between two adjacent second plurality of fin structures in the second region and an isolation structure formed on the substrate. The isolation structure has a gap height between the first plurality of fin structures and the second plurality of fin structures.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yi-Cheng Chao, Chai-Wei Chang, Po-Chi Wu, Jung-Jui Li
  • Publication number: 20190148241
    Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate, and the substrate includes a first region and a second region. The FinFET structure includes a first plurality of fin structures formed on the first region and a second plurality of fin structures formed on the second region. A density of the first plurality of fin structures is greater than a density of the second plurality of fin structures. The FinFET structure also includes a plurality of protruding structures between two adjacent second plurality of fin structures in the second region and an isolation structure formed on the substrate. The isolation structure has a gap height between the first plurality of fin structures and the second plurality of fin structures.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yi-Cheng CHAO, Chai-Wei CHANG, Po-Chi WU, Jung-Jui LI
  • Publication number: 20190140333
    Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: TZONG-LIN WU, PO-JUI LI, YING-CHENG TSENG, CHI-HSUAN CHENG
  • Patent number: 10269963
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20190102717
    Abstract: Methods and systems associated with a microservice based predictive service level agreement (SLA) impact analytics system that may run on standardized container based virtual computing platform to enable capacity auto-scaling for on-demand, near-real-time resource allocation automatically supporting user data packet forwarding when SLA is potentially impacted to ensure SLA compliance.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Tsong-Ho Wu, Wen-Jui Li, Jun-Min Liu
  • Publication number: 20190081869
    Abstract: Concepts and technologies disclosed herein are directed to context-aware virtualized control decision support system (“DSS”) for providing quality of experience (“QoE”) assurance for Internet protocol (“IP”) streaming video services. A QoE assurance DSS can monitor QoE event and context data to be utilized for QoE assurance analytics, measure QoE performance, perform QoE assurance analytics, and determine whether the QoE assurance analytics indicate that the QoE has been degraded, and if so, construct a fault correlation information model to be utilized for root cause analysis to determine a root cause of the QoE being degraded. The QoE assurance DSS also can determine, based upon the fault correlation information model, whether the root cause of the QoE being degraded is due to a capacity reduction, and if so, the QoE assurance DSS can identify a new network resource for capacity reallocation to accommodate a virtual machine migration.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 14, 2019
    Applicant: AT&T Intellectual Property I, L.P.
    Inventors: Tsong-Ho Wu, Wen-Jui Li
  • Publication number: 20190081879
    Abstract: Concepts and technologies disclosed herein are directed to an auto-scaling software-defined monitoring (“SDM”) platform for software-defined networking (“SDN”) service assurance. According to one aspect of the concepts and technologies disclosed herein, an SDM controller can monitor event data associated with a network event that occurred within a virtualized IP SDN network that is monitored by a virtualized SDM resources platform. The SDM controller can measure, based upon the event data, a quality of service (“QoS”) performance metric associated with the virtualized SDM resource platform. The SDN controller can determine, based upon the QoS performance metric, whether an auto-scaling operation is to be performed. The auto-scaling operation can include reconfiguring the virtualized SDM resources platform by adding virtual machine capacity for supporting event management tasks either by instantiating a new virtual machine or by migrating an existing virtual machine to a new hardware host.
    Type: Application
    Filed: November 14, 2018
    Publication date: March 14, 2019
    Applicant: AT&T Intellectual Property I, L.P.
    Inventors: Tsong-Ho Wu, Wen-Jui Li, Hasan Erkan
  • Patent number: 10211496
    Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 19, 2019
    Assignee: National Taiwan University
    Inventors: Tzong-Lin Wu, Po-Jui Li, Ying-Cheng Tseng, Chi-Hsuan Cheng
  • Patent number: 10148489
    Abstract: A service impact event analyzer is used to evaluate service assurance risk in cloud SDN networks. Using data fusion, an alarm subset dataset is generated from a raw trap dataset. Service impact events are identified in the subset dataset. The service impact events are categorized into service impacted event categories, and a model is created for associating the event categories with process function classes. Time durations of the service impact events are computed using correlated secondary alarms from the alarm subset dataset. The service assurance risk is evaluated using the model and the time duration.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: December 4, 2018
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Tsong-Ho Wu, Wen-Jui Li, Shyhyann Lee, Li-Chuan Sun
  • Publication number: 20180337246
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 10135701
    Abstract: Concepts and technologies disclosed herein are directed to context-aware virtualized control decision support system (“DSS”) for providing quality of experience (“QoE”) assurance for Internet protocol (“IP”) streaming video services. A QoE assurance DSS can monitor QoE event and context data to be utilized for QoE assurance analytics, measure QoE performance, perform QoE assurance analytics, and determine whether the QoE assurance analytics indicate that the QoE has been degraded, and if so, construct a fault correlation information model to be utilized for root cause analysis to determine a root cause of the QoE being degraded. The QoE assurance DSS also can determine, based upon the fault correlation information model, whether the root cause of the QoE being degraded is due to a capacity reduction, and if so, the QoE assurance DSS can identify a new network resource for capacity reallocation to accommodate a virtual machine migration.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: November 20, 2018
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Tsong-Ho Wu, Wen-Jui Li
  • Patent number: 10135712
    Abstract: Concepts and technologies disclosed herein are directed to an auto-scaling software-defined monitoring (“SDM”) platform for software-defined networking (“SDN”) service assurance. According to one aspect of the concepts and technologies disclosed herein, an SDM controller can monitor event data associated with a network event that occurred within a virtualized IP SDN network that is monitored by a virtualized SDM resources platform. The SDM controller can measure, based upon the event data, a quality of service (“QoS”) performance metric associated with the virtualized SDM resource platform. The SDN controller can determine, based upon the QoS performance metric, whether an auto-scaling operation is to be performed. The auto-scaling operation can include reconfiguring the virtualized SDM resources platform by adding virtual machine capacity for supporting event management tasks either by instantiating a new virtual machine or by migrating an existing virtual machine to a new hardware host.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: November 20, 2018
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Tsong-Ho Wu, Wen-Jui Li, Hasan Erkan
  • Publication number: 20180316594
    Abstract: An IP network topology update system may update IP network topology in near real-time and on-demand with minimum overheads. It identifies likely impact area (e.g., layer 2 or layer 3), objects (e.g., link or node such a device), and timing (e.g.
    Type: Application
    Filed: April 27, 2017
    Publication date: November 1, 2018
    Inventors: Tsong-Ho Wu, Wen-Jui Li, Wai Lai
  • Patent number: 10090396
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao