Patents by Inventor Jui Li

Jui Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100765
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20240247365
    Abstract: Apparatus and methods for multi-cathode barrier seed deposition for high aspect ratio features in a physical vapor deposition (PVD) process are provided herein. In some embodiments, a PVD chamber includes a pedestal disposed within a processing region of the PVD chamber. The pedestal rotates with a workpiece on it. The PVD chamber includes a lid assembly includes a first target and a second target of a same target material, where a first surface of the first target defines a first zone of the processing region a first distance from the upper surface of the pedestal, and a second surface of the second target defines a second zone of the processing region a second distance from the plane of the upper surface of the pedestal. A system controller is configured to simultaneously control a first voltage bias for the first target and a second voltage bias for the second target.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Inventors: Harish V. PENMETHSA, Ming-Jui LI
  • Publication number: 20240222454
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI
  • Patent number: 12027488
    Abstract: Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 2, 2024
    Assignees: The Regents of the University of California, Wayne State University, Georgia Tech Research Corporation
    Inventors: Mike Breeden, Victor Wang, Andrew Kummel, Ming-Jui Li, Muhannad Bakir, Jonathan Hollin, Nyi Myat Khine Linn, Charles H. Winter
  • Patent number: 11967628
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: April 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li
  • Publication number: 20240038690
    Abstract: A semiconductor device includes an electronic device, a guard trace and a first trace. The guard trace is connecting to a ground layer through a first ground via. The first trace is disposed adjacent to the electronic device and the guard trace and includes a first segment. A phase or a direction of a first current signal conducted on the first trace is changed in the first segment. The electronic device and the first trace are disposed at different sides of the guard trace and the first ground via is beside the first segment.
    Type: Application
    Filed: June 19, 2023
    Publication date: February 1, 2024
    Applicant: MEDIATEK INC.
    Inventors: Po-Jui Li, Ruey-Bo Sun, Yen-Ju Lu, Chun-Yuan Yeh, Sheng-Mou Lin
  • Publication number: 20240040769
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI, Chih-Yu YEN
  • Publication number: 20230395689
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Application
    Filed: July 25, 2023
    Publication date: December 7, 2023
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 11832435
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li, Chih-Yu Yen
  • Publication number: 20230353653
    Abstract: The present disclosure relates to a system, a method and a computer-readable medium for notification of a live streaming program. The method includes obtaining a list of users related to the live streaming program, obtaining a first contribution score of a first user in the list of users, and transmitting a first notification request for notifying the first user about the live streaming program according to the first contribution score. The first contribution score is determined according to a behavior of the first user. The present disclosure can result in a more reliable notification, which may further improve the operation of a live streaming platform.
    Type: Application
    Filed: October 31, 2022
    Publication date: November 2, 2023
    Inventors: Hong Dian CHEN, Hsing Yu TSAI, Jui LI
  • Publication number: 20230352549
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 2, 2023
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI
  • Patent number: 11764280
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 11742402
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: August 29, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Hsu-Cheng Fan, En-Jui Li
  • Publication number: 20230208728
    Abstract: A cloud gateway outage risk detector can receive, by an event listener module, user session data associated with a plurality of user sessions over a cloud gateway. The event listener module can store the data in a database. A run-time collection module can obtain at least a portion of the data. The run-time collection module can provide the portion of the data to a run-time risk criteria evaluation module that can determine, based upon the portion of the data, a run-time outage risk criteria for the cloud gateway. A baseline risk criteria evaluation module can obtain historical data from the database. The baseline risk criteria evaluation module can determine, based upon the data, a baseline outage risk criteria for the cloud gateway. The run-time risk criteria evaluation module can determine whether the run-time outage risk criteria meets or exceeds an outage risk threshold.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Applicant: AT&T Intellectual Property I, L.P.
    Inventors: Zosim Kanevsky, Wen-Jui Li
  • Publication number: 20230157001
    Abstract: A method of fabricating the semiconductor device includes forming a bit line structure over a substrate, forming a spacer structure on a sidewall of the bit line structure, partially removing an upper portion of the spacer structure to form a slope on the spacer structure slanting to the bit line structure, forming a landing pad material to cover the spacer structure and contact the slope, and removing at least a portion of the landing pad material to form a landing pad against the slope.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI, Chih-Yu YEN
  • Publication number: 20230119022
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Patent number: 11601344
    Abstract: A cloud gateway outage risk detector can receive, by an event listener module, user session data associated with a plurality of user sessions over a cloud gateway. The event listener module can store the data in a database. A run-time collection module can obtain at least a portion of the data. The run-time collection module can provide the portion of the data to a run-time risk criteria evaluation module that can determine, based upon the portion of the data, a run-time outage risk criteria for the cloud gateway. A baseline risk criteria evaluation module can obtain historical data from the database. The baseline risk criteria evaluation module can determine, based upon the data, a baseline outage risk criteria for the cloud gateway. The run-time risk criteria evaluation module can determine whether the run-time outage risk criteria meets or exceeds an outage risk threshold.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 7, 2023
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Zosim Kanevsky, Wen-Jui Li
  • Publication number: 20230021814
    Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.
    Type: Application
    Filed: July 21, 2021
    Publication date: January 26, 2023
    Inventors: Chih-Wei HUANG, Hsu-Cheng FAN, En-Jui LI
  • Patent number: 11532748
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20220216578
    Abstract: The invention discloses a filter device. The filter device comprises a substrate, at least one transmission conductor, and a reference conductor having a slotted structure. The substrate is provided at a first surface thereof with the transmission conductor, and provided at a second surface thereof with the reference conductor. The slotted structure comprises a frame portion, a slotted portion, and a hollow portion. The slotted portion surrounds the frame portion, and the hollow portion is formed in the frame portion. At least one impedance unit is configured on the frame portion. The equivalent filter circuit of the filter device is formed between the transmission conductor, the slotted structure, the reference conductor, and the impedance unit. Thereby, the equivalent filter circuit absorbs at least one noise at at least one specific frequency by the impedance unit to avoid the noise reflected to affect the transmission quality of signal.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 7, 2022
    Inventors: TZONG-LIN WU, HSU-WEI LIU, CHI-HSUAN CHENG, PO-JUI LI