Abstract: An electronic device includes: a body, including opposite outer and inner surfaces, and a through opening passing through the outer and inner surfaces; a fan, disposed on the outer surface and having an air outlet; a heat sink assembly, disposed at the air outlet and corresponding to the through opening; a first thermal tube, having one end assembled on the heat sink assembly and located on the side of the outer surface; a first heat source, disposed corresponding to the other end of the first thermal tube; a thermal plate, disposed in the body and corresponding to the through opening, having one side abutting against the heat sink assembly and the inner surface; a second thermal tube, having one end connected to the other side of the thermal plate; and a second heat source, disposed corresponding to the other end of the second thermal tube.

Abstract: An assembly is provided for an aircraft propulsion system. This assembly includes an engine core, a bypass duct and a bleed circuit. The engine core includes a compressor section, a combustor section, a turbine section and a core flowpath extending sequentially through the compressor section, the combustor section and the turbine section. The bypass duct includes a bypass flowpath outside of the engine core. The bleed circuit includes a bleed passage and a flow regulator. The bleed circuit is configured to direct bypass gas through the bleed passage from the bypass flowpath into the core flowpath when the flow regulator is in an open position. The bleed circuit is configured to cutoff gas flow through the bleed passage between the bypass flowpath and the core flowpath when the flow regulator is in a closed position.

Abstract: A semiconductor structure includes a capacitor structure and a contact structure. The capacitor structure includes an electrode layer, a protective dielectric layer, and a capacitor dielectric layer. The protective dielectric layer covers a top surface of the electrode layer. The capacitor dielectric layer is on the protective oxide layer. The contact structure penetrates the protective oxide layer and electrically connects to the electrode layer.

Abstract: A motherboard module includes a motherboard assembly and an insertion piece. The motherboard assembly includes a motherboard, an electrical connector, a first sealing component and a second sealing component. The electrical connector is disposed on the motherboard. The first sealing component is disposed on the motherboard and located around a periphery of the electrical connector. The second sealing component is disposed on the first sealing component. The insertion piece has an insertion portion. The insertion portion is inserted into the electrical connector, and the second sealing component and the first sealing component cover the electrical connector and the insertion portion of the insertion piece together.

Abstract: Semiconductor structures and methods for fabricating semiconductor structures are provided. A semiconductor structure includes a first fin extending in an X-direction and a second fin parallel to the first fin and distanced from the first fin in a Y-direction perpendicular to the X-direction. Each fin is formed with a first device area and a second device area aligned in the X-direction; an isolation region disposed between the fins; an isolation structure disposed between the device areas in each fin; and an isolation layer disposed under the fins. The isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin from the second fin and to isolate the first device area from the second device area in each fin.

Abstract: An image capturing system includes six lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The fourth lens element has positive refractive power, the object-side surface of the fourth lens element is concave in a paraxial region thereof, and the image-side surface of the fourth lens element is convex in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one lens element of the image capturing system has at least one inflection point in an off-axis region thereof.

Abstract: A riser cage assembly having a riser cage bracket and a fastener assembly coupled to the riser cage bracket is disclosed. The fastener assembly includes an enclosure, an actuator including drivers, a shaft, and a biasing member. The enclosure has a bore, guide teeth within the bore, and bays defined between the guide teeth. The actuator is movably coupled to an end of the enclosure with the drivers disposed within the bore. The shaft has blades disposed within the bore, and a locking arm protruding beyond the bore from another end of the enclosure. The actuator generates biasing force urging the shaft towards the end of the enclosure. The shaft is translatable along and rotatable along a vertical axis relative to the enclosure, by the actuator and the biasing member to removably fasten the riser cage bracket to the electronic device.

Abstract: Optical devices and methods of manufacture are presented in which glass interposers are incorporated with optical devices. In some embodiments a method includes forming a first optical package and then bonding the first optical package to a first glass interposer. The first glass interposer may then be connected to a second interposer.

Abstract: One aspect of the present disclosure pertains to a device. The device includes a memory macro having a frontside and a backside along a vertical direction. The memory macro includes edge strap areas extending lengthwise along a first direction at edges of the memory macro, a memory cell area having a plurality of memory cells, where the memory cell area is disposed between the edge strap areas along a second direction perpendicular to the first direction, and a middle strap area extending lengthwise along the first direction and disposed between the edge strap areas along the second direction, where the middle strap area divides the memory cell area into two memory cell domains. The middle strap area includes a feedthrough circuit that routes a power signal line of one of the plurality of memory cells to the backside of the memory macro.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element. In a plan view, the active region includes a first portion and a second portion narrower than the first portion. The method also includes removing the first semiconductor layers of the first active region. The second semiconductor layers of the first portion of the first active region form first nanostructures, and the second semiconductor layers of the second portion of the first active region form second nanostructures. The method also includes forming a first gate stack to surround the first nanostructures, and forming a second gate stack to surround the second nanostructures.

Abstract: A semiconductor structure according to the present disclosure includes a first memory cell that includes a first pull-down transistor and a first pull-up transistor sharing a first gate structure extending along a first direction, a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the first direction, a first pass-gate transistor having a third gate structure spaced apart but aligned with the second gate structure along the first direction, and a second pass-gate transistor having a fourth gate structure spaced apart but aligned with the first gate structure along the first direction, a frontside interconnect structure disposed over the first memory device, a backside interconnect structure disposed below the first memory device. A source of the second pull-down transistor is electrically coupled to the backside interconnect structure by way of a first backside contact via.

Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: A semiconductor device according to the present disclosure includes a memory array having a plurality of memory cells arranged in a row, and an interconnect structure disposed over the memory cells and having a bit line coupled to each of the memory cells arranged in the row. The bit line has a first segment coupled to a first portion of the memory cells and a second segment coupled to a second portion of the memory cells. The first segment has a first width and the second segment has a second width that is smaller than the first width.

Abstract: The present invention relates to an LC medium comprising two or more polymerizable compounds, at least one of which contains a substituent comprising a tertiary OH group, to its use for optical, electro-optical and electronic purposes, in particular in LC displays, especially in LC displays of the PSA (polymer sustained alignment) or SA (self-aligning) mode, to an LC display of the PSA or SA mode comprising the LC medium, and to a process of manufacturing the LC display using the LC medium, especially an energy-saving LC display and energy-saving LC display production process.

Abstract: An imaging lens assembly includes three lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element and a third lens element. Each of the three lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the second lens element is concave in a paraxial region thereof. At least one surface of at least one lens element in the imaging lens assembly has at least one inflection point.

Abstract: An optoelectronic module, including a substrate, a covering member, a light emitting element, and a light receiving element, is provided. The covering member is disposed on the substrate and includes an upper cover portion, a peripheral sidewall portion connected to the upper cover portion, and an inside partition delimiting a first cavity and a second cavity. The first cavity is separated from the second cavity. The light emitting element is disposed on the substrate as corresponding to the first cavity. The light receiving element is disposed on the substrate as corresponding to the second cavity. The inside partition has a first inner wall surface located in the first cavity and a second inner wall surface located in the second cavity. A first protruded-recessed structure is formed on the first inner wall surface.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a gate structure. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line are positioned at a first interconnect layer disposed over the gate structure and a read word line positioned at a second interconnect layer and electrically coupled to the gate structure, the second interconnect layer is disposed under the gate structure.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source/drain feature and a second source/drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source/drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source/drain feature.

Abstract: An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

Abstract: An intraoral phototherapy device for simultaneously irradiating inner and outer gingiva includes a transparent shell and a circuit board. The transparent shell includes a bite portion and a stop portion. The bite portion is mounted on an inner arc surface of the stop portion. The circuit board is mounted in the bite portion, and includes first and second light emitting units. The first and the second light emitting units emit lights toward a first and a second surface of the bite portion. When a user bites the bite portion and turn on the intraoral phototherapy device, the lights emitted by the first and the second light emitting units are emitted to a gum inside and outside upper and lower jaw teeth of the user. Therefore, the intraoral phototherapy device can stimulate an affected part of a gingivitis through a photobiomodulation therapy to achieve an effect of anti-inflammation or alleviating pain.