Abstract: The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction.

Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

Abstract: An electronic device having a detachable memory is provided with a docking connector, and includes a device body and a memory. The device body has an accommodating slot and a stopping portion provided corresponding to the accommodating slot, and the stopping portion and the accommodating slot jointly form a displacement space in between. The memory is provided with a connector and a protruding stopped portion. When the memory is accommodated in the accommodating slot, the stopped portion is moved along into the displacement space and is stopped by the stopping portion, and the connector is docked with the docking connector. Thus, the memory is provided with an anti-misplugging effect.

Abstract: A compound including a first ligand LA of is disclosed. In the structure of Formula I, one of L1 and L2 is C, and the other is N; Y1 to Y14 are each C or N; at least two adjacent Y7, Y8, Y9, and Y10 are carbon atoms that are fused to a structure of Z1 and Z2 are each O, S, Se, NR, CRR?, or SiRR?; and each R, R?, RA, RB, RC, and RD is hydrogen or a substituent; and any two substituents may be joined or fused together to form a ring. In the compound, LA is complexed to a metal M by L1 and L2, and M has an atomic weight greater than 40. Organic light emitting devices and consumer products containing the compounds are also disclosed.

Abstract: An imaging lens assembly includes six lens elements which are, in order from an object side to an image side along an optical path: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has positive refractive power. The image-side surface of the fourth lens element is convex in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one lens element of the imaging lens assembly has at least one critical point in an off-axis region thereof.

Abstract: A method includes following steps. A first gate dielectric layer is deposited over a first semiconductor channel and a second semiconductor channel. A second gate dielectric layer is deposited over the first gate dielectric layer. A layer is formed over the second gate dielectric layer using atomic layer deposition (ALD) cycles each comprising sequentially performing a first pulse step for a first pulse time, a first purge step for a first purge time, a second pulse step for a second pulse time, and a second purge step for a second purge time. A ratio of the first purge time to the first pulse time is greater than a ratio of the second purge time to the second pulse time. The layer is patterned to expose a portion of the second gate dielectric layer. The exposed portion of the second gate dielectric layer is etched.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: Provided are organometallic compounds comprising iridium as a central metal atom which is coordinated by two three-dentate ligands which each comprise at least three 5-membered or 6-membered rings. Also provided are formulations comprising these organometallic compounds. Further provided are organic light emitting devices (OLEDs) and related consumer products that utilize these organometallic compounds.

Abstract: Disclosed are a conductive film and a test component. A conductive film includes a supporting layer, a circuit layer and a protective layer. The supporting layer has a first surface and a second surface opposite to the first surface. The supporting layer supports the circuit layer. The circuit layer includes a first protruding part, a second protruding part and a connecting part. The first protruding part is disposed on the first surface. The second protruding part is disposed on the second surface. The connecting part is disposed between the first protruding part and the second protruding part. The first protruding part is connected to the second protruding part through the connecting part. The protective layer covers the first protruding part. The conductive film and the test component of the disclosed embodiments may have a buffering effect or increase the service life.

Abstract: A photonic semiconductor device including a light-emitting component and a photonic integrated circuit is provided. The light-emitting component at least includes a gain medium layer, a first contact layer and a first optical coupling layer stacked to each other. The photonic integrated circuit includes a second optical coupling layer. The light-emitting component and the photonic integrated circuit are stacked in a stacking direction, the first optical coupling layer has a first taper portion, the second optical coupling layer has a second taper portion, and the first taper portion and the second taper portion overlap in the stacking direction. Accordingly, the light emitted from the gain medium layer may be transmitted to the second taper portion from the first taper portion by optical coupling in a short length of an optical coupling path.

Abstract: A method for controlling a derailleur in low battery remaining capacity includes determining whether a remaining capacity of a first battery of the derailleur is smaller than or equal to a first derailleur battery threshold. When the remaining capacity of the first battery is determined to be smaller than or equal to the first derailleur battery threshold, at least one of gear positions of the derailleur is invalided and non-selectable by the derailleur.

Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.

Abstract: A projection device including a casing, a light source module, an optical engine module and a projection lens is provided. A front cover, a rear cover, a first side cover, a second side cover, an upper cover and a lower cover of the casing surround an accommodating space. The light source module includes a first and a second light sources, and a first and a second light source heat dissipation modules. The lower cover has a first, a second and a third air inlets. The first and the second side covers respectively have a first and a second air outlets. The first and the second light source heat dissipation modules are correspondingly disposed above the first air inlet and correspond to the first air outlet. The second and the third air inlets are respectively disposed below two sides of the projection lens and adjacent to the front cover.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.

Abstract: A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.

Abstract: A backlight module and a display device are provided, and the backlight module includes a light guide plate, a plurality of light-emitting components, and a frame. The light guide plate includes a first side, a second side, and two third sides. The light-emitting components are disposed on the first side, and light generated from the light-emitting components enters the light guide plate from the first side. The frame covers the second side and the third sides and includes an opening and at least one buffer portion. The light-emitting components are disposed in the opening, and the buffer portion is disposed on a side of the opening and contacts the light guide plate.