Patents by Inventor Jui Lin

Jui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12111446
    Abstract: An optical imaging system includes four lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements of the optical imaging system has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the first lens element is concave in a paraxial region thereof, and the image-side surface of the first lens element is convex in a paraxial region thereof. The object-side surface of the fourth lens element is convex in a paraxial region thereof, the image-side surface of the fourth lens element is concave in a paraxial region thereof, and the image-side surface of the fourth lens element has at least one convex shape in an off-axis region thereof.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: October 8, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu Jui Lin, Hsin-Hsuan Huang
  • Patent number: 12113081
    Abstract: The package structure having packaged components within includes a circuit board, multiple packaged light detecting components mounted on the circuit board, a sealing cap being light transmittable, multiple light filtering films mounted on the sealing cap, and a supporting annular wall. The two opposite ends of the supporting annular wall are adhesively bonded to the surfaces of the circuit board and the sealing cap, such that the projection on the circuit board of the light filtering films corresponds the packaged light detecting components. Since the light filtering films have different filtering frequency bands, each packaged light detecting component detects light of different frequency bands in one incident light beam. The package method is simple and stable, effectively lowering the manufacture cost of the light detecting module.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 8, 2024
    Assignee: TAIWAN REDEYE BIOMEDICAL INC.
    Inventors: Shuo-Ting Yan, Chen-Chung Chang, Tsung-Jui Lin
  • Publication number: 20240332089
    Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
  • Publication number: 20240324245
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Shih-Hao LIN, Po-Sheng LU, Chenchen Jacob WANG, Yuan Hao CHANG, Ping-Wei WANG
  • Patent number: 12100360
    Abstract: The present disclosure provides a backlight module and a display device. The backlight module includes a light source structure and an optical film. The light source structure includes a substrate, plural light-emitting units and a package structure. The light-emitting units are disposed on the substrate. The package structure covers the light-emitting units, and the package structure has plural convex portions. The optical film is disposed on the light source structure, and the optical film is in contact with the convex portions of the package structure.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: September 24, 2024
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Jui-Lin Chen, Pin-Hsun Lee, Yuan-Jhang Chen, Che-Kai Chang, Chun-Hung Ho, Hung-Yi Chen
  • Patent number: 12093629
    Abstract: A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells, the method including generating the layout diagram including: for a candidate cell amongst the layout cells in the layout diagram, avoiding a discrete calculation of a corresponding parasitic capacitance (PC) description including, within a database which stores predefined cells and corresponding parasitic capacitance (PC) descriptions thereof, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and, when a substantial match is found, assigning the PC description of the matching predefined cell to the candidate cell.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Ze-Ming Wu, Po-Jui Lin
  • Publication number: 20240304659
    Abstract: Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.
    Type: Application
    Filed: May 15, 2024
    Publication date: September 12, 2024
    Inventors: Hsing-Lien Lin, Jui-Lin Chu, Cheng-Yuan Tsai
  • Publication number: 20240306359
    Abstract: A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.
    Type: Application
    Filed: August 3, 2023
    Publication date: September 12, 2024
    Inventors: Ping-Wei Wang, Feng-Ming Chang, Jui-Lin Chen
  • Publication number: 20240306361
    Abstract: A semiconductor structure includes a memory cell, a logic cell, and a transition region between the memory cell and the logic cell. The memory cell includes a first active region and a plurality of first gate structures with a gate pitch. The logic cell includes a second active region and a plurality of second gate structures with the gate pitch. The transition region includes a first dielectric feature and a second dielectric feature. The first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region. The second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region.
    Type: Application
    Filed: July 10, 2023
    Publication date: September 12, 2024
    Inventors: Ping-Wei Wang, Lien-Jung Hung, Jui-Lin Chen
  • Publication number: 20240306358
    Abstract: A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.
    Type: Application
    Filed: August 3, 2023
    Publication date: September 12, 2024
    Inventors: Ping-Wei Wang, Feng-Ming Chang, Jui-Lin Chen
  • Publication number: 20240304240
    Abstract: A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.
    Type: Application
    Filed: July 12, 2023
    Publication date: September 12, 2024
    Inventors: Ping-Wei Wang, Feng-Ming Chang, Jui-Lin Chen
  • Publication number: 20240306362
    Abstract: A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.
    Type: Application
    Filed: August 9, 2023
    Publication date: September 12, 2024
    Inventors: Ping-Wei Wang, Feng-Ming Chang, Jui-Lin Chen
  • Patent number: 12079407
    Abstract: A touch sensor includes a substrate, sensing channels, and a protective layer. The sensing channels are disposed at intervals on a surface of the substrate, and any one of the sensing channels includes an electrode portion and a silver trace portion electrically connected to the electrode portion. The protective layer is disposed on the substrate and covers and encapsulates the sensing channels. After the touch sensor is subjected to a salt spray test with sodium chloride solution of a mass percentage concentration of 5% at a rate of 1 mL/H to 2 mL/H under an ambient temperature of 35° C. for 48 hours, a resistance change rate of any one of the sensing channels is less than or equal to 10%, and a resistance distribution difference between the sensing channels is less than or equal to 10%.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: September 3, 2024
    Assignee: TPK Advanced Solutions Inc.
    Inventors: Shao Jie Liu, Si Qiang Xu, Chien Hsien Yu, Chia Jui Lin, Jian Zhang, Wei Na Cao, Mei Fang Lan, Jun Hua Huang, Mei Fen Bai, Song Xin Wang
  • Publication number: 20240292590
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 29, 2024
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 12068575
    Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a light-transmissive conducting layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has multiple holes to form a photonic crystal structure. The insulating layer is over an upper surface and a sidewall surface of the first platform, and over an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, and the active layer. The light-transmissive conducting layer connects to the photonic crystal structure through an aperture of the insulating layer. The first electrode has an opening corresponding to the aperture. The second electrode is under the substrate.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 20, 2024
    Assignee: PHOSERTEK CORPORATION
    Inventors: Yu-Chen Chen, Chien-Hung Lin, Bo-Tsun Chou, Chih-Yuan Weng, Kuo-Jui Lin
  • Publication number: 20240272352
    Abstract: A method includes connecting a first photonic package to a substrate, wherein the first photonic package includes a first waveguide and a first support over the first waveguide; connecting a second photonic package to the substrate adjacent the first photonic package, wherein the second photonic package includes a second waveguide, wherein the first photonic package and the second photonic package are laterally separated by a gap that has a width in the range of 15 ?m to 190 ?m; depositing a first quantity of an optical adhesive into the gap; and curing the first quantity of the optical adhesive, wherein after curing the first quantity of the optical adhesive, the first waveguide is optically coupled to the second waveguide through the first quantity of the optical adhesive.
    Type: Application
    Filed: May 26, 2023
    Publication date: August 15, 2024
    Inventors: Chen-Hua Yu, Tsung-Fu Tsai, Chih-Hao Yu, Jui Lin Chao, Szu-Wei Lu
  • Patent number: 12038379
    Abstract: A sanitary device for the urine glucose test includes a urine container formed on an inner wall of a main body, and a measuring module with an inner space mounted at a bottom of the urine container. Within the inner space, a lens attaches to the bottom of the urine container, a rail faces a bottom surface of the lens, and a driving module moves a light unit shooting a detection beam to a measuring surface of the lens along the rail. The measuring surface contacts urine in the urine container, and reflects the detection beam out of the bottom surface into a sensor. The sensor is electrically connected to a processor. The processor determines a urine glucose level and generates a urine glucose level data instantly from an angle of incidence of the detection beam on the measuring surface and from a beam intensity signal from the sensor.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan RedEye Biomedical Inc.
    Inventors: Shuo-Ting Yan, Tsung-Jui Lin, Yu-Hsun Chen, Kuan-Wei Su
  • Publication number: 20240231044
    Abstract: An imaging system lens assembly includes eight lens elements which are, in order from an object side to an image side along an optical path, a first lens element through an eighth lens element. The first lens element has negative refractive power. The object-side surface of the first lens element is concave in a paraxial region thereof and has at least one inflection point in an off-axis region thereof. The eighth lens element has positive refractive power. The object-side surface of the eighth lens element is convex in a paraxial region thereof. The image-side surface of the eighth lens element is concave in a paraxial region thereof and has at least one inflection point in an off-axis region thereof. At least one of the lens surface of at least one of the second through seventh lens elements has at least one inflection point in an off-axis region thereof.
    Type: Application
    Filed: March 24, 2023
    Publication date: July 11, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Yu Jui LIN, Tzu-Chieh KUO
  • Publication number: 20240219981
    Abstract: An electronic device having a detachable memory is provided with a docking connector, and includes a device body and a memory. The device body has an accommodating slot and a stopping portion provided corresponding to the accommodating slot, and the stopping portion and the accommodating slot jointly form a displacement space in between. The memory is provided with a connector and a protruding stopped portion. When the memory is accommodated in the accommodating slot, the stopped portion is moved along into the displacement space and is stopped by the stopping portion, and the connector is docked with the docking connector. Thus, the memory is provided with an anti-misplugging effect.
    Type: Application
    Filed: March 12, 2024
    Publication date: July 4, 2024
    Inventors: Jui-Lin YANG, Juei-Chi Chang
  • Patent number: 12028099
    Abstract: A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: July 2, 2024
    Assignee: MEDIATEK INC.
    Inventors: Jui-Lin Hsu, Hsiang-Yun Chu, Yen-Tso Chen, Jen-Hao Cheng, Wei-Hsiu Hsu, Tzu-Chin Lin, Chih-Ming Hung, Jing-Hong Conan Zhan