Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first active region in forming a first transistor. The second gate structure engages the second active region in forming a second transistor. The first and second transistors have a same conductivity type. The memory cell further includes a first epitaxial feature on a source region of the first transistor, a second epitaxial feature on a source region of the second transistor, a first frontside contact directly above and in electrical coupling with the first epitaxial feature, a second frontside contact directly above and in electrical coupling with the second epitaxial feature, and a first backside via directly under and in electrical coupling with one of the first and second epitaxial features with another one of the first and second epitaxial features free of a backside via directly thereunder.

Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively, and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. A first frontside source/drain contact is disposed above and electrically couples to a first common source/drain region of the first and second pull-down transistors. A first backside via is disposed under and electrically couples to the first common source/drain region. A first backside metal line is disposed under and electrically couples to the first backside via.

Abstract: At a topology controller, a method may: receive a topology request at the topology controller, based at least partially on the topology request, select an input-output (I/O) link connecting an input node to a destination node from a plurality of I/O links including at least: a direct I/O link between the input node and the destination node, and a switched I/O link between the input node and the destination node, and configure an active I/O link between the input node and the destination node based on the selected I/O link.

Abstract: Apparatus and methods for power amplifier output matching is disclosed. In one aspect, there is provided an output matching circuit including an input configured to receive an amplified radio frequency signal from a power amplifier, a first output, and a second output. The output matching circuit further includes a first matching circuit electrically connected between the input of the output matching circuit and the first output, the first matching circuit configured to suppress harmonics of a fundamental frequency of the amplified radio frequency signal when the amplified radio frequency signal is within a first band. The output matching circuit further includes a second matching circuit electrically connected between the input of the output matching circuit and the second output, the second matching circuit configured to suppress harmonics of the fundamental frequency of the amplified radio frequency signal when the amplified radio frequency signal is within a second band different from the first band.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively. The second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. The memory cell also includes a first source/drain contact via electrically coupled to the first and second pull-down transistors, a second source/drain contact via electrically coupled to the first and second pull-up transistors, a first gate contact electrically coupled to the first gate structure, and a second gate contact electrically coupled to the second gate structure. One of the first and second source/drain contact vias has an area larger than either of the first and second gate contacts in a top view of the memory cell.

Abstract: A semiconductor structure includes a substrate, first channel layers vertically stacked over the substrate in a first region, and second channel layers vertically stacked over the substrate in a second region. The first and second regions have opposite conductivity types. The semiconductor structure also includes a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers in the second region. The first region is free of the Vt modulation layer. The semiconductor structure also includes a gate dielectric layer wrapping around each of the first channel layers and the second channel layers over the Vt modulation layer, and a work function metal layer disposed on the gate dielectric layer and wrapping around each of the first channel layers and the second channel layers.

Abstract: A method (of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells) comprises generating the layout diagram including: reusing one amongst predefined parasitic capacitance (PC) descriptions of corresponding predefined cells that are stored within a database, the reusing including: for a candidate cell amongst the layout cells in the layout diagram, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and when a substantial match is found, reusing the PC description of the matching predefined cell by assigning the same to the candidate cell rather than otherwise making a discrete calculation of a corresponding PC description for the candidate cell.

Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has a photonic crystal structure. The insulating layer is disposed on an upper surface and a sidewall surface of the first platform, and on an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, the active layer, and at least a portion of the first waveguiding layer. The first electrode is on the insulating layer and the second electrode is connected to the outer surface of the substrate and arranged to form an opening for laser output.

Abstract: An assembly may comprise a mounting tray configured to have at least one printed circuit board mounted to its top surface and further comprises a set of spools extending from an outer surface of the first mounting tray, each spool including a barrel and a flange. The assembly may comprise a base pan including a set of keyholes, each keyhole including an entry hole and a slot extending from the entry hole. The base pan is configured to attach to the mounting tray by engaging the set of spools with a group of keyholes, respectively, by inserting the flange of each spool through the entry hole of a corresponding keyhole and moving the mounting tray relative to the base pan such that the barrel of each spool is received within the slot, and the flange of each spool of the set of spools is secured by a rim of the slot of the corresponding keyhole.

Abstract: An optical photographing lens assembly includes seven lens elements which are, in order from an object side to an image side along an optical path, a first lens element through a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the second lens element is convex in a paraxial region thereof. The sixth lens element has positive refractive power. The object-side surface of the seventh lens element is convex in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one of the seven lens elements has at least one inflection point in an off-axis region thereof.

Abstract: The package structure having packaged components within includes a circuit board, multiple packaged light detecting components mounted on the circuit board, a sealing cap being light transmittable, multiple light filtering films mounted on the sealing cap, and a supporting annular wall. The two opposite ends of the supporting annular wall are adhesively bonded to the surfaces of the circuit board and the sealing cap, such that the projection on the circuit board of the light filtering films corresponds the packaged light detecting components. Since the light filtering films have different filtering frequency bands, each packaged light detecting component detects light of different frequency bands in one incident light beam. The package method is simple and stable, effectively lowering the manufacture cost of the light detecting module.

Abstract: An optical imaging system includes four lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements of the optical imaging system has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the first lens element is concave in a paraxial region thereof, and the image-side surface of the first lens element is convex in a paraxial region thereof. The object-side surface of the fourth lens element is convex in a paraxial region thereof, the image-side surface of the fourth lens element is concave in a paraxial region thereof, and the image-side surface of the fourth lens element has at least one convex shape in an off-axis region thereof.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

Abstract: The present disclosure provides a backlight module and a display device. The backlight module includes a light source structure and an optical film. The light source structure includes a substrate, plural light-emitting units and a package structure. The light-emitting units are disposed on the substrate. The package structure covers the light-emitting units, and the package structure has plural convex portions. The optical film is disposed on the light source structure, and the optical film is in contact with the convex portions of the package structure.

Abstract: A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells, the method including generating the layout diagram including: for a candidate cell amongst the layout cells in the layout diagram, avoiding a discrete calculation of a corresponding parasitic capacitance (PC) description including, within a database which stores predefined cells and corresponding parasitic capacitance (PC) descriptions thereof, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and, when a substantial match is found, assigning the PC description of the matching predefined cell to the candidate cell.

Abstract: A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.

Abstract: A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.

Abstract: A semiconductor structure includes a memory cell, a logic cell, and a transition region between the memory cell and the logic cell. The memory cell includes a first active region and a plurality of first gate structures with a gate pitch. The logic cell includes a second active region and a plurality of second gate structures with the gate pitch. The transition region includes a first dielectric feature and a second dielectric feature. The first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region. The second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region.